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Fig. 1: Temperature inversion. Design teams gradually took on more of the responsibilities of signoff work from the ASIC vendors as they moved production to foundries. At the same time, layout-dependent effects played an increasing role in the performance of design. Gate delay moved to become less important on critical paths. Wire delay took over as the key issue to solve. This called for a new generation of layout-aware tools developed by both large, broad-based EDA tools suppliers and start-ups. Start-ups played a crucial role with their technology. Each could tackle a hole in the offerings of mainstream suppliers by, very often, recruiting a small and select group of ‘teaching customers’ who could feed back vital information on tool performance from real designs. Engineers from these start-ups would often engage in close collaboration with the design teams inside the customers responsible for benchmarking and working with their software. In recent years, many of the nanometer effects with which SoC design teams must engage have become closely interconnected. Just ten years ago, a timing violation on a critical path could easily have been solved by the insertion of a buffer, or the movement of some of the gates to reduce the wire distance and with it delay. A point tool optimized for this analysis and solution could easily be inserted into a broader design flow. Analysis was often optimized for capacity rather than accuracy. As designs moved to millions of gates, runtime overhead was often the primary issue. Parasitics could, to a large extent, be abstracted out except for paths that were extremely close to the timing margin. At 130nm, for example, the gap between metal interconnect lines were such that their coupling capacitances were overshadowed by ground and pin capacitance. For the inter-track coupling capacitance, it was generally easier and faster to add a small margin. The number of timing runs was also quite limited. In general, it was sufficient to analyze a best-case, nominal and worstcase scenario for three of the key parameters: process, voltage and temperature. This would effectively encompass all the realistic operating points for the design on its target process. It was reasonable to make the assumption that delay would be at maximum temperature, lowest voltage and worst process conditions. As process dimensions shrank, assumptions that previously held up well began to break down. The coupling capacitance between metal interconnect became much more significant at 65nm because the line pitch was much tighter and the traces themselves became taller in order to keep parasitic resistance under control. As a result, the lines began to behave more like the parallel plates of a capacitor. At 45nm, the variation in metal thickness became a key concern, increasing the range over which designs needed to be simulated to provide best-case and worst-case delay values. Below 45nm, lithographically-induced variations in transistor, gate and local interconnect structures became significant, leading to the introduction of larger margins to accommodate the difference across the process variability range. Other, more subtle, effects of the shift to nanometer dimensions have led to an explosion in the effort needed to achieve timing signoff. The overarching issue is the interaction between global and local effects. Since the beginning of the past decade, behavior under temperature changes became more difficult to predict, a situation that has been given the name “temperature inversion dependence”. The issue is caused by the use of lower supply voltages in order to provide greater energy efficiency – see figure 1. Instead of running faster than a ‘hot’ corner, the circuitry may run more slowly under a certain threshold voltage as the temperature falls – and the effect is dependent on the threshold voltage used in the devices that lie along the path being analyzed. The reason for the effect is that two effects combine to determine the delay through a logic gate. At the higher voltages used traditionally, mobility controls the drain current of an active transistor. But as voltages drop, the threshold voltage has a much larger role in determining drain current. As a result, old assumptions break down and demand that a larger number of analyses are needed to check properly for variations. In nanometer processes, variability is more localized than it was on older processes. Metal line widths have become small enough to impact the resistance of the wire with just a small amount of variation. Given that metallization is a separate process from base layer processing, engineers cannot assume that process variations will move in the same direction for both base and metal layers. Therefore, at 45nm and to a larger extent at 28nm, multiple extraction corners were required for timing analysis and optimization. Double patterning provides further source of variability in sub-28nm processes. Because lithography under double patterning calls for two masks for the same layer, the masks must be precisely aligned such that the spacing between patterns is consistent across the die. Although foundries are working hard to minimize the effect, there will always be some phase shift in the masks relative to each other and it may not be possible to predict what that phase shift is – see figure 2. Timing views are required that reflect the impact of phase shifts in different direc- Fig. 2: Mask shift occurs with double patterning. www.electronics-eetimes.com Electronic Engineering Times Europe July/August 2013 21


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