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EETE JULAUG 2013

EDA & DESIGN TOOLS Fig. 3: Trend of analysis views (MxC) at shrinking nodes. Fig. 4: Aggregrate runtime with increasing views. tions for a given combination of temperature, voltage and other process variations. The focus on low-energy design adds a further layer of complexity in timing signoff. Designs that employ techniques such as dynamic frequency and voltage scaling in order to optimize their energy efficiency will need to be analyzed at multiple operating points to ensure that effects such as temperature dependence inversion do not adversely affect the timing reliability of the SoC. These analyses should be performed against the other sources of variability, leading to a combinatorial explosion. With just eight different operating modes, it is easy to reach the situation where more than 200 timing views need to be analyzed. Through careful selection and pruning of the combinations – removing those that are unlikely to provide significantly different results to other tests – it is possible to reduce the number. But the SoC implementation team is still left with a large number of timing views to generate - see figure 3. The problem is not just confined to the leading-edge processes. Increasingly, low-power design techniques are being applied to designs aimed at older processes. Although these processes will have fewer sources of variability, as voltages are reduced to take advantage of power savings, effects such as temperature dependence inversion become more apparent. The time it takes to generate each timing view is only a small part of the problem. Up to 40 per cent of the chip implementation flow is now consumed by the time it takes to act on the results of the analyses – see figure 4. Each timing view generates a set of violations that need to be correlated with the results from the other timing views. Consolidating the data takes time, engineering insight and, for many teams today, custom scripts to process the data. There is then the issue of implementing the changes needed to close timing. Today’s signoff timers are not physically aware. Any changes, such as buffer insertion, are left to the implementation environment as a post-processing step for engineering change order (ECO) generation. Often the placement of new cells is dramatically different from what is assumed by the optimization algorithms because available vacant space is hard to find in highly utilized designs. The result is a significant mismatch between the assumed interconnect parasitics during the optimization steps and the actual placement and routing that result from the ECO. Changes may affect the timing of paths that may have already met timing, causing them to violate timing in the timing views from the subsequent iteration. What previously may have been a timingclean view could potentially have many violations after placement and rerouting. One thing becomes clear from an analysis of the way in which timing signoff has evolved over the past decade. A simple technology update is not enough to solve the problems. Conventional wisdom holds that startups provide much of the innovation for technologically driven markets. Startups have traditionally used ‘teaching customers’ to help drive them towards market-ready solutions. However, such solutions do not always make it to market because the need is no longer for narrowly defined solutions but for a tool infrastructure that cuts across the different pieces of the implementation flow. A more accurate implementation engine would reduce some of the overhead of dealing with multiple timing views. But a genuine solution requires attention to multiple points in that flow, involving a more holistic approach. There are numerous actors in the SoC ecosystem who can and do provide essential knowledge and feedback on issues that affect design and implementation. It is extremely difficult for a start-up with a more restricted set of partners to engage with all of them in order to derive the best solution. Although the core technology being delivered may have many strong points and provide better support for certain issues, the key today is to be able to bring all of the technology to build a more cohesive solution. It involves input from foundries and IDMs, with their knowledge of the way that variability issues affect timing. Library vendors have their part to play in understanding the issues caused by moves to smaller geometries and the impact of technologies such as double patterning. And there are the early adopter customers who can provide real-world designs that exercise all parts of a design flow. Then there is the role of the EDA tools supplier to bring the inputs together and develop new ways of dealing with the influx of data. The supplier needs to have the scope to look at the flow in a holistic manner and understand which are the chokepoints that limit design speed. A more accurate implementation engine for ECOs is one possible answer to the problem of timing signoff. But a more effective approach may be to look at the overarching requirements of signoff and to work out ways in which the application of timing fixes and ECOs are made so that they are more closely integrated with the timing signoff process. That requires a combination of new technology and attention to detail in the architecture of the overall flow that a player with decades of experience in implementation can bring. As a result, the industry is moving towards a new development pipeline that involves a matrix of partnerships rather than individual links between design and tools-development groups. By bringing these different views together, EDA tools developers can react much more quickly to the needs of design and reflect the pace of innovation that is taking place in product design and process engineering. 22 Electronic Engineering Times Europe July/August 2013 www.electronics-eetimes.com


EETE JULAUG 2013
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