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EETE JULAUG 2013

Modeling skew requirements for interfacing protocol signals in an SoC By Hans Kumar Jain, Gourav Kapoor and Babul Anunay A system on a chip (SoC) today consists of several different microprocessor subsystems, memories and support for I/O interfaces such as JTAG, Ethernet, DSPI, SENT etc for communication with the outside world – see figure 1. All these are universally accepted and have some timing requirements which may be in form of input/output delay requirements or special timing requirements (like transition and skew requirements for different signals), which need to be taken care of at the STA end. In this article, we will be focusing on one of these – maximum and minimum skew between two signals. Some of these protocols (like DDR) have requirement for a finite maximum skew (difference in delays) between the various signals of a bus. All data has to change within a very small timing window. On the contrary, minimum skew requirement is generally specified to prevent the race condition between two signals. This is usually one sided; e.g. signal ‘a’ should follow ‘b’ after some finite time. Until recently, these skew requirements were modeled in a roundabout manner and had to be updated regularly which adversely impacted the STA analysis time of each database as there were multiple iterations for IO constraints maturity. Also, the constrained signals’ timing may get deteriorated during optimization in the absence of constraints on these signals. There can be different ways of implementing this using multiple command combinations. Each has its own merits and demerits. Let’s look at three methods to achieve this purpose: Hans Kumar Jain is Lead Design Engineer at Freescale Semiconductor India - www.freescale.com Gourav Kapoor and Babul Anunay also work at Freescale Semiconductor India as Design Engineers. CircularConnAd-EETimesEurope_Layout 1 6/25/13 4:41 PM Page 1 Fig. 1: SoC interfacing with the outside world through I/O protocols. - Applying minimum/maximum delay constraints on data signals - Modeling as input/output delays - Applying setup/hold checks considering one of the data signals as reference signal Applying minimum/maximum delay constraints We can apply min and max delay constraints on data signals so that data changes only within a given window. This method can be used to constrain multiple signals for skew requirement as discussed below. We are essentially assuming these signals to circular connectors specialty emi filtered & unfiltered • Vertically integrated – we make our own planar and tubular capacitors, shells, shields, seals and grommets • Highest quality and the industry’s shortest lead times (8-10 weeks, std) • MIL and Hi-Rel connectors • Rapid mate “hot shoe” and mini-MIL circular connectors • Our EMI expertise gives you a better filtered connector • Harnessing products to IPC-A-610 and J-STD-001 • 100% testing of all vital electrical parameters • Broad range of ITAR free filtered and unfiltered circular connectors available Download our capabilities brochure & video Call +49.9122.795.0 or visit eis.apitech.com EMI Filters • EMI Filtered Connectors • Ceramic Capacitors • Power Filter Capacitors • Magnetics www.electronics-eetimes.com Electronic Engineering Times Europe July/August 2013 23


EETE JULAUG 2013
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