EDA & DESIGN TOOLS Fig. 2: Constraining signals to be within window by applying min/max delays. have some characteristic delay range, which is a pure assumption or based on prior experience. The EDA command to apply min/max delay is: set_min_delay/set_max_delay <delay_value> signal A data bus can be constrained to be within a specific window by constraining each bit signal with min and max delays (where max_delay > min_delay) – see figure 2. set_min_delay <min_delay_value> data_bus* set_max_delay <max_delay_value> data_bus* The maximum skew requirement window will then be: Max_skew_requirement = Max_delay_value – Min_delay_ value Similarly, the timing requirement for minimum skew can be justified by applying max_delay constraint to one signal (the one which is to occur first) and min_delay constraint to the other (the one which is to occur later – see figure 3). set_max_delay <smaller_value> signal_1 set_min_delay <larger_value> signal_2 Where: Min_skew_requirement = Min_delay_value – Max_delay_ value The application of min/max delays offers some advantages, the uncertainty values applied on path don’t need to be taken into account and delays can be modified in any of the data signal path as long as the above conditions are met. This method, however, faces some limitations as it takes a couple of iterations to decide upon the values of the min-max delay. Fig. 4: Constraining signals to be within window by applying input/output delays. It is important to keep the values slightly pessimistic (compared to the expected optimized value of delay) in the first iteration so as to efficiently optimize the path delay as well. The values need to be updated as well after such iteration based on how much the tool was able to optimize the delay. Also, the values need to be updated at regular intervals as we make transitions across the stages since delay values change. As delays of nets and cells scale across process, voltage and temperature variations, min/max path delays will be different across these. We have to calculate scaling factors across corners and constrain these accordingly. Constraining IOs by modeling input/output delays In this method, we define the relationship of interface signals with respect to some clock. We may use it to implicitly define skew requirement by defining input/output delays of different signals with respect to same clock such that they are constrained to have the required skew. Basically, by defining input and output delays, we are defining setup and hold timings of the signals in the SoC as seen from the outer world. The designer just needs to constrain these by defining valid and invalid windows. I/Os may be constrained in EDA tools using the following commands: set_input_delay/set_output_delay <delay_value> port_ name –min/-max To constrain signals to be within a timing window (maximum skew requirement) using this technique, we need to define setup and hold checks (min and max input delays) for all signals with respect to the same clock such that all signals are allowed to change nowhere except the required window - as shown in figure 4. Considering both signals to be input signals, max_input_delay = clock_period –setup_requirement min_input_delay = hold_requirement Under the condition setup_check_for_signal1 + hold_check_for_signal2 < clock_period & setup_check_for_signal2 + hold_check_for_signal1 < clock_period Similarly, we can constrain the signals for minimum skew requirement. For this, following condition should be kept in mind (for signal1 to follow signal2 – see figure 5): Setup_check_for_signal1 + hold_check_for_signal2 > clock_period Fig. 3: Constraining signals for minimum skew by applying min/max delay constraints. 24 Electronic Engineering Times Europe July/August 2013 www.electronics-eetimes.com

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