Encart Microchip

EETE JULAUG 2013

EDA & DESIGN TOOLS System builder design tool targets ARM-based SmartFusion2 SoC FPGAs Microsemi’s System Builder is a new design tool within the Libero System-on-Chip (SoC) Design Environment version 11.0 and is specifically targeted at accelerating customer definition and implementation of ARM-based systems using SmartFusion2 SoC FPGAs. The output from System Builder is automatically generated and correct-by-construction, thus eliminating the errors that are created when the architecture is specified ‘by hand’ as in more traditional tool flows. Thus, System Builder dramatically shortens the design cycle time for complex SoC FPGAs. Additionally, software-oriented engineers can easily create an embedded architecture and begin code development all on their own. This simplifies the adoption of Microsemi SmartFusion2 devices and provides a much broader set of design engineers with access to SoC FPGA technology. System Builder users are guided step-bystep through each of the main SoC FPGA architecture blocks. The design process uses a high-level graphical Interface that reacts to previous architecture selections and guides the user through the process of selecting options and configuring only the required embedded system blocks. The resulting system specification is automatically generated and correct– by-construction. It includes both the configuration and interconnects of the ARM processor and its related peripherals as well as other IP blocks implemented in the FPGA fabric. System Builder can also configure a growing set of IP blocks for high-performance interfaces including DDR2/DDR3/LPDDR memory controllers, and serial interfaces using 5Gbps SERDES for PCIe, XAUI (10 GbE) and SGMII. Additional fabricbased parameterized IP functions available within System Builder include I2C, SPI, Timers, UARTs and PWM blocks. SmartFusion2 integrates inherently reliable flash-based FPGA fabric, a 166MHz ARM Cortex-M3 processor, advanced security processing accelerators, DSP blocks, SRAM, eNVM and industry-required high performance communication interfaces. Microsemi www.microsemi.com Revised IEEE 1149.1 ‘JTAG’ standard should reduce IC design costs through test re-use IEEE has released the revised IEEE 1149.1-2013 “Standard for Test Access Port and Boundary-Scan Architecture” (JTAG). This revision is intended to dramatically lower electronics industry costs by enabling test re-use across all phases of the integrated circuit lifecycle via vendor-independent, hierarchical test languages. The revision of IEEE 1149.1, the first for the standard since 2001, allows critical domain expertise for intellectual property (IP)—how to configure a serializer/deserializer (SERDES) for loopback testing, for example—to be transferred in a computerreadable format from the IP designer to IC designers and, in turn, to designers of printed circuit boards (PCBs) and to test engineers, gradually magnifying industry cost savings along the supply chain. The cost savings for the electronics industry that IEEE 1149.1-2013 is intended to unlock are estimated to be in the billions of dollars. IEEE 1149.1-2013 specifies a new hierarchical Procedural Definition Language (PDL)—a standard test language based on Tcl, and hierarchical extensions to the original Boundary Scan Description Language (BSDL) to describe on-chip IP test data registers. Eight new optional IC instructions provide a foundation for configuring I/Os for board test, mitigating false failures when re-testing the IC at the board level and correlating the results back to wafer level test through an Electronic Chip ID. Now, the IP provider can document the IP test Interface and how to operate the IP in an English-like language—just once, for all ICs. Software tools then re-target this documentation at the IC and board level for tests. In revising IEEE 1149.1, the working group focused on two things: lowering industry costs through the new PDL language and enabling test re-use over the lifecycle of an integrated circuit. IEEE 1149.1-2013 provides critical synergy with two other important industry standards. IEEE 1149.1-2013 supports segmented on-chip test data registers that cross power domains specified by IEEE 1801-2013 “Standard for Design and Verification of Low Power Integrated Circuits”. IEEE 1149.1-2013 enables descriptions and operation of IP accessible via IEEE 1500-2005 “Standard Testability Method for Embedded Corebased Integrated Circuits” structures. IEEE www.ieee.org Debug probe supports Infineon’s single-pin debug interface Segger has added support for Infineon’s Single Pin Debug (SPD) Interface for Infineon’s XMC1000-series to the J-Link family of debug probes. The J-Link is, Segger asserts, the only commercial debug probe in the market capable of connecting to a device with the SPD-interface. “Support for Infineon’s SPD-interface makes J-Link even more versatile”, according to Segger, “We are making sure our complete line of J-Link debug probes support all major tool vendors, CPU architectures and target interfaces and the first vendor supporting Infineon’s XMC1000 series singlewire debug Interface is just one more point of proof”. “The SEGGER support for the SPD-interface significantly improves the eco-system for the XMC1000-series. By working with SEGGER, the SPD-interface is now accessible from all popular tool-chains in the market, including the free DAVE development platform and other free GDB-based development environments,” says Dr. Stephan Zizala, Senior Director, Industrial and Multimarket Microcontrollers at Infineon Technologies. The SEGGER J-Link debug probe on the market is tool chain independent and works with commercial IDEs from: Atmel, Atollic, Coocox, Freescale, IAR, i-Systems, ImageCraft, KEIL, Mentor Graphics, Phyton, Rowley, Renesas, Tasking and others, as well as free GDB-based tool chains such as emIDE and EmBlocks. J-Link supports multiple CPU families, such as ARM 7, 9, 11, Cortex-M0, M0+, M1, M3, M4, R4, A5, A8, A9 as well as Renesas RX610, 620, 62N, 62T, 630, 631, 63N; there is typically no need to buy a new J-Link or new license when switching to a different CPU family or toolchain. Segger www.segger.com/jlink.html 26 Electronic Engineering Times Europe July/August 2013 www.electronics-eetimes.com


EETE JULAUG 2013
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