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EETE JULAUG 2013

EDA tool optimises cell libraries for processor cores in SoCs Synopsys has announced a physical-IP design kit optimised for SoC processor cores; the DesignWare HPC Design Kit yields superior performance, power and area for CPU, GPU and DSP Cores Synopsys has announced an extension to its DesignWare Duet Embedded Memory and Logic Library IP portfolio specifically designed to enable the optimised implementation of a broad range of processor cores. The new Design- Ware HPC (High Performance Core) Design Kit contains a suite of high speed and high density memory instances and standard cell libraries that allow system on chip (SoC) designers to optimise their on chip CPU, GPU and DSP IP cores for maximum speed, smallest area or lowest power – or to achieve an optimum balance of the three for their specific application. Synopsys developed in collaboration with partners including Imagination Technologies, CEVA and VeriSilicon. The tool operates in conjunction with the synthesis stage of a design flow (in a flow where the synthesis is aware of floorplanning issues), and is in part empirical; based on studies of “what works best” when implementing logic structures typical of processor cores, it selects and lays down specific standard cell variants when it recognises certain features of processor logic, improving speed, power and silicon area. It includes around 125 new cells and memory elements. Initially focused on TSMC’s 28-nm HPM process, Synopsys says it will produce variants for other processes at that node, including lowpower versions; 16-nm fin-FET processes are a further possible target, and the company “may” look back at 40-nm processes if demand exists. The optimisation package uses standard “Liberty” syntax. Synopsys www.synopsys.com/hpc-ip System planner tool automatically generates 3D mechanical constraints Zuken has released new versions of its System Planner and Design Gateway engineering solutions that accelerate and streamline product planning and logical design for engineers. System Planner includes new functions that allow design architects to study behaviour, signal quality, and 3D space constraints. Design Gateway includes improvements for hierarchy, rule checking, and an Intel Schematic Connectivity Format (ISCF) format for Intel design review. Zuken has streamlined the design flow for real-world engineering design, embedding multiboard SI analysis into System Planner. This permits engineers to study behaviour and signal quality of system-level interconnections during the early design planning stage. It also facilitates “what-if” analysis to capture optimal topology and termination schemes earlier in the design process. Additionally, by importing accurate 3D enclosure and component models, engineers can create board outlines, see component profiles, and automatically generate mechanical constraints (such as height restrictions) for multi-board floor planning. Enhanced design reuse supports drag-and-drop of logical and physical data from the reuse library directly in System Planner. These can be fed directly into the design flow with Design Gateway (logical design) and Design Force (physical design). Design Gateway’s Circuit Advisor, part of Zuken’s schematic engineering environment, includes new rule checks to support multi-board design for physical connector mismatches, I/O checks to ensure proper continuity between boards, and checks for duplicate references throughout the system. Simplified classification of nets and constraint entry allow users to define complex spacing requirements for High-Speed interfaces such as PCI Express and DDR2/3/4. Zuken www.zuken.com Automated software-driven verification tool Vayavya Labs has released SOCX-Verifier, claimed to be the EDA industry’s first software-driven verification tool that automatically generates verification test software and relevant testbench components from a system-level scenario specification. With SOCX-Verifier, SoC designers can now bridge and greatly accelerate the arduous hardware-software co-design process. While there are flows that are based on virtual platforms and emulation platforms, there is still a huge amount of effort and cost involved in developing embedded software for SoCs. SOCX-Verifier provides all the necessary building blocks for driver-model generation, scenario specification and virtualizing test-bench interaction to give verification teams a speedier closure and effective system-level verification. Further this also enables the software developers to deliver production ready software drivers at a 10x efficiency level, according to Vayavya Labs. Softwaredriven verification methodology harnesses the embedded processor core’s power to verify the SoC from “Inside-Out.” SOCX-Verifier provides verification designers with the required infrastructure and building blocks for driver-model generation, scenario specification and virtualizing test-bench interaction for a speedier closure and effective system-level verification. It consists of two main components: SOCXSpecifier and SOCX-Virtualizer. SOCXSpecifier brings the canvas for capturing the scenario specifications and generates C test cases from this specification. The C test cases execute on the embedded processor core(s) in the SoC and access the designunder test (DUT) components (design IP blocks) and the test-bench. SOCX-Virtualizer virtualizes access to the DUT components as well as the test-bench across various verification platforms. It achieves this by means of a “verification aware” lightweight operating system (OS) and the DDGen tool which automatically generates device drivers for the DUT components. Vayavya Labs www.vayavyalabs.com www.electronics-eetimes.com Electronic Engineering Times Europe July/August 2013 27


EETE JULAUG 2013
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