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EETE JULAUG 2015

CEO interview Memory IP and going below 28nm Memory and memory interfaces are part of Cadence’s IP, courtesy of the acquisition of Denali Software but that does not mean Cadence expects to do basic research in non-volatile memory technologies, even though there is a technology gap to be filled at the 28nm logic node. “The carbon nanotube memory looks interesting, but does it have mainstream foundry support?” asked Tan, referring to the carbon nanotube based non-volatile memory technology being developed by Nantero Inc. (Woburn, Mass.). “If it became an industry standard we would support it.” Tan said that in terms of process miniaturization there is a clear divergence going on between Cadence customers that want to go down to 10nm and beyond and others that are content to work at 28nm or higher nodes. “That’s why 28nm is going to be a long-lived node. And that’s because 16/14nm may not bring any cost gains. The only reason to move down to these lower nodes is performance,” said Tan. “Video and graphics push performance and so will move down; mixed-signal can stay with 28nm.” Tan said he does have customers pushing for 16/14nm process and 10nm. “We are working on 10nm and 7nm. We need to be there.” The wave of complexity that this will bring was one of the reasons that Cadence undertook a major rewrite of its IC tools to equip them for massive parallel processing. This means they are able to scale to meet the challenge of leading edge design with billions of transistors. But collaborative design is also fundamental to getting working chips at reasonable yield at these advanced nodes, said Tan. Part of that is in terms of reducing cost by sharing engineering. Often that involves a four-source team drawn from the customer, the EDA vendor, the IP provider and the foundry. That might typically be the customer plus, ARM, Cadence and TSMC although many other combinations are also possible and have to be supported. One implication is that not all possible combinations can be supported. Automotive on the move One result of the changing landscape is that automotive IC design, generally thought of being mixed-signal and conservative because of the need to meet robustness and reliability issues is moving down through the nodes faster than before to 40nm, where embedded non-volatile memory is available, to 28nm and The Cadence IP factory covers the three vital ingredients of digital systems, processors, memory, and I/O. Source: Cadence, IMEC Technology Forum. even on to 16nm FinFET designs. This is partly because of the increasing infotainment content in the relatively benign cabin environment of the automobile, but particularly because of the phase of rapid design for ADAS (automotive driver assistance systems) that is now going on. These ADAS designs are dominated by video and graphical information flows and require high-performance processing to make decisions rapidly, said Tan. Whither FDSOI? Does fully-depleted silicon on insulator (FDSOI), an alternative manufacturing style to the FinFET that uses simpler manufacturing on SOI wafers, have a place to play in the chip making universe? FDSOI has not been embraced by two of the largest chip manufacturers Intel and TSMC, although Samsung has agreed to be volume manufacturer for developer of the FDSOI process STMicroelectronics. “There is some merit to FDSOI in terms of power. At 28nm/20nm some customers are using FDSOI for some special circuits. It is also being looked at for RF,” said Tan. “We have worked with STMicroelectronics and the tools are ready,” said Tan. “We follow where the customer goes,” Tan said. The overall message from Lip-Bu Tan is that while a move up to the system level may not be completely apparent, it is happening. “We call it system design enablement,” said Tan. At the same time the company is spanning an ever-broader range of complexity from nanoscale physics to 4G and 5G communications protocols and to do so must engage in even higher levels of collaboration. Imec looks forward to life after FinFET By Graham Prophet Imec is presenting concepts for successors to FinFET, for fabrication geometries of 7nm and beyond, at the VLSI Technology Symposium 2015 At the VLSI 2015 Symposium in Kyoto (Japan), imec has reported new results on nanowire FETs and quantum-well FinFETs towards post-FinFET multi-gate device solutions. As the major portion of the industry adopts FinFETs as the “workhorse” transistor for 16nm and 14nm, researchers worldwide are looking into the limits of FinFETs and potential device solutions for the 7nm node and beyond. Two approaches, namely Gate-All- Around Nanowire (GAA NW) FETs, which offer significantly better short-channel electrostatics, and quantum-well FinFETs (with SiGe, Ge, or IIIV channels), which achieve high carrier mobility, are promising options. For the first time, imec demonstrated the integration of these novel device architectures with state-of-the-art technology modules such as Replacement-Metal-Gate High-k (RMG-HK) and Self (Spacer)-Aligned Double-Patterned (SADP) dense fin structures. By building upon today’s advanced FinFET technolo- 10 Electronic Engineering Times Europe July-August 2015 www.electronics-eetimes.com


EETE JULAUG 2015
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