Page 22

EETE JULAUG 2015

Semi packaging tech Wafer-level packaging is not enough, say OSATS GBy Julien Happich athering a crowd of IC packaging and semiconductor processing experts in Vila do Conde, Portugal, European’s largest provider of Outsourced Semiconductor Assembly and Test Services (OSATS) Nanium S.A. hosted this year’s SEMI Packaging Tech Seminar at its headquarters, concluding the keynote sessions with a fab tour. The focus of the discussions there was on large format fan-out packaging, or the necessity that OSATS felt, under yield and packaging cost pressures, to move from Fan-Out Wafer-Level-Packaging (FO-WLP) to Fan-Out Panel-Level-Packaging (FOPLP). First highlighting the market drivers for FO-WLP, TechSearch International’s president E. Jan Vardaman pointed out how year-on-year mobile devices got thinner and thinner by adopting an increasing number of wafer level packages for their electronic content. She illustrated this with seven generations of iPhones, thinning from around 12mm to 7mm while increasing their WLP content from 2 dies to over 26 dies. The conventional WLPs trends, she said, include higher I/O counts and larger dies. And together with shrinking geometries, the number of I/Os per die dramatically increased over the years from a few dozens to well over 400, calling for multi-die packages or a move to larger FO-WLP where the I/Os can be distributed not only underneath the die but at the package’s periphery (like extra margins surrounding the die). Typically, FO-WLP benefit from the same thinness (under 0.4mm) but can integrate multiple dies from different technology nodes, as well as some passives. Nanium offered a good example by moulding together two active dies and 10 surfacemounted passives within a 9x8mm package. According to TechSearch, FO-WLP could reach over 1.8 billion units per year in 2019, versus less than 300 million packages shipped in 2014. But then, if the trend is to continue, the real-estate on reconstituted wafers will become the limiting factor for optimized larger package integration and cost efficiency, since the piece count remains limited or is even reduced (as the packages grow) on a wafer-like substrate. As the declining average selling price for end products creates further price pressure, it drives OSATS to develop lower cost package options too, moving to large area packaging beyond today’s wafer sizes. “This is where the wafer fab side, back end assembly, and PCB segments are merging” she said. Citing a few examples of panel-sized FO-WLP R&D efforts up to 610x457mm2, Vardaman concluded that panel-based processing has a promising future despite the numerous technical challenges it brings with it. These challenges, just to name a few, include large panel manipulation (new infrastructures moving the dies from wafer-level processing machines to larger panel-capable equipment), die placement accuracy across large panels, panel warpage and new dispensing processes altogether to achieve sufficient molding uniformity and planarity. Some solutions put forward by Fraunhofer IZM revolve around so-called compression molding, using either a mold-first approach or a redistribution layer-first approach. In principle, it looks fairly simple. A glob of encapsulation compound is poured onto the reconstituted wafer before it is compressed by a panel mould, under vacuum and temperature, until it fills all the interstices between the dies. Fraunhofer IZM’s Deputy Group Manager for Assembly and Encapsulation, Tanja Braun discussed her results comparing liquid, granular and sheet lamination molding compounds. While the paste-like liquid compounds may require complex dispensing patterns to optimize flow, the granular material exhibited the most promising results, as it can be distributed nearly homogeneously all over the cavity before it melts during the compression cycle. It also came out as the most economical with no dispensing limitations for large areas (also faster to dispense than a paste). When homogeneously spread, the granular material investigated didn’t suffer from the flow marks and knit lines that liquid compounds yielded (regardless of the numerous dispensing patterns investigated). The lab then went on to mold 250μm thin dies on 610x457mm2 panels (24”x18”) with a mold thickness of 450μm, concluding that although FO-PLP is feasible, there is no simple upscaling of technologies from Fig. 1: iPhone Trends: Increasing Number of WLPs. Source: TechSearch International. Fig. 2: Nanium’s multiple die Fan-Out package integration with passives. Fig. 3: Fraunhofer IZM’s molding process, relying on Apic Yamada’s LPM-600 manual (semi-auto) molding system (for panels up to 670x620mm²). 22 Electronic Engineering Times Europe July-August 2015 www.electronics-eetimes.com


EETE JULAUG 2015
To see the actual publication please follow the link above