Page 6

EETE JULAUG 2015

memory shrink Inside 1X nm Planar NAND By Kevin Gibb NAND flash makers have started selling their 1X nm class of planar flash memory. Planar NAND flash may not make it past 10nm node, but here’s a look inside 15/16nm, analyzed by TechInsights. Over the last year and a half, the major NAND flash makers have started selling their 1X nm class of planar flash memory. According to our sourcing of the devices on the open market, summarized in Table 1, Micron was first with product appearing in February of 2014, followed by SK-Hynix in October. Table 1: TechInsights Receipt of 1X nm Class NAND Flash Nearly 6 months later, products sporting Samsung 16nm or Toshiba 15nm NAND flash showed up in our laboratories. There has been much discussion in the literature on the end of lithographic scaling of planar NAND flash, and its replacement with vertically stacked flash such as Samsung’s 3D V-NAND or Toshiba’s BiCS. There is a consensus that planar NAND will end near the 10 nm node, that is, one or two generations into the future from the 15/16 nm NAND flash that we at TechInsights are now completing analysis on. We thought it timely to look at some process features that we see in these 15/16 nm flash memories. We have been buying NAND flash memory for a number of years for our technical analysis reports and figure 1 shows the process nodes versus year that we acquired them for Micron and SK-Hynix. These two manufacturers Fig. 1: Observed process nodes for Micron and Hynix NAND Flash vs. Year (Source: TechInsights) were typically the first to market with a process node. A semi-log plot is used to show the roughly 23%/year process shrink (solid black line) that we see for the Micron and Hynix devices. The rate of process shrinks has slowed dramatically for the 25 nm and smaller product and this likely reflects the difficulties in implementing double patterning lithography and reducing electrical interference between adjacent cells. Two approaches can be used for double patterning. Litho-etch-litho-etch (LELE) double patterning (DP) that is typically used for logic processes, or self-aligned double patter-ning (SADP) using sidewall spacers that is used by the memory makers. This has worked for NAND flash devices down to the present 16 nm node but may not make it to the 10 nm class of devices. But scaling down to planar 10 nm NAND flash is still seen as a significant challenge and this has spurred efforts to develop 3D vertical NAND flash memory. For completeness, we include Samsung’s 3D V-NAND in figure 1 as it is the first Fig. 2: Self aligned double commercially available part. patterning process. Toshiba, Hynix and Micron will likely introduce their 3D NAND product in the near future. Double patterning patterning has become mandatory for making the 16 nm node NAND flash and the memory makers use a self-aligned double patterning (SADP) for the active, control gate, floating gate and bitline patterning. The SADP process sequence from making the initial pattern, through the sidewall spacer etch back to the double pattern transfer is shown schematically in figure 2. The double patterning process can often result in an asymmetry in the spaces between the final sidewall spacer structures that is seen as an AB patterning. And this is readily seen in the STI patterning of the Micron 16 nm NAND flash shown in figure 3. A tungsten metal word line is seen running left to right overtop a series of planar floating gate structures that are aligned to the underlying silicon channels. The floating gates and silicon channels have been patterned and etched together using a SADP process. The bottoms of the shallow trench isolation (STI) between adjacent silicon channels exhibit the characteristic AB pattern in their etch depths, indicating the use of a selfaligned double patterning process. SK-Hynix used a quad spacer patterning for their M1X nm floating gate NAND presented at IEDM 2013 and this is likely being used for their 16 nm NAND flash shown in figure 4. The AB pattern at the bottom of the trenches is largely absent being replaced with a more random patterning. We see similar random patterning with the Samsung 16 nm and Toshiba 15 nm NAND flash memories, perhaps indicating that they too are using a Kevin Gibb is Product Line Manager at TechInsights - www.techinsights.com Fig. 3: Micron 16 nm NAND flash Si channels and STI (Source: TechInsights) 6 Electronic Engineering Times Europe July-August 2015 www.electronics-eetimes.com


EETE JULAUG 2015
To see the actual publication please follow the link above