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Fig. 4: Hynix 16 nm NAND flash Si channels and STI (Source: TechInsights) Fig. 5: SK-Hynix 16 nm NAND control gate wrap (Source: TechIn sights) quad spacer patterning process. The next design problem is to maintain a high capacitive coupling between the control gate and floating gate, while minimizing the capacitive coupling between adjacent cells. Traditionally, the control gate (CG) is wrapped around three sides of the floating gate (FG) as shown in figure 5. The interpoly dielectric (IPD) provides the capacitive coupling between the CG and FG and it needs to have excellent blocking characteristics to current and a high dielectric constant k. Hynix’s oxide/nitride/oxide (ONO) layers can be seen in figure 5. The IPD is fairly thick and this reduces the gap for the control gate fill between the adjacent floating gates. Hynix has thinned down the sides of the floating gates to provide more room for the control gate. But the opportunities for continued shrinking of the NAND cell pitch in this direction is limited if one wants to maintain the control gate over the three sides of the floating gate. We note that Hynix has added air gaps between the silicon channels (active air gap) to reduce their capacitive coupling. Micron has eschewed the wrap-around control gate in favour of a planar control/floating gate structure for their 16 nm NAND flash. This is not their first time for using a planar gate structure, as we also observed it in Micron’s 20 nm NAND flash memory. The gate structure is shown in Figure 6. Micron has retained the polysilicon floating gate but it is now quite thin. This allows the HfO2/oxide/HFO2 interpoly dielectric layers to lie nearly flat overtop the floating gate, and the very high dielectric constant of the HfO oxide layers yields sufficient capacitive coupling between the control and floating gates to eliminate the need for the gate wrap around structures that are used by Fig. 6: Micron 16 nm NAND Control Gate Wrap (Source: TechInsights) Hynix, Samsung and Toshiba. Shrinking of the word line and bitline pitches has exacerbated the capacitive coupling between adjacent cells. This is a problem as the programmed state of the one cell can be capacitively coupled to the adjacent cell. This can result in disturbed cell threshold voltages (VT) and misread bits. Air gaps between adjacent word lines have been used for a number of years to reduce their capacitive coupling and figure 7 shows an example of this used by Toshiba for their 1st generation 15 nm NAND flash. The floating gate air gaps used by the Samsung 16 nm NAND are shown in Figure 8. These air gaps are much less uniform that Toshiba’s. This would suggest that the Samsung cells will show a greater variability in cell-to-cell cross-talk and this might show up as increased overhead for the cell write and erase times. Air gaps are not confined to active substrate and word lines as Micron has adopted air gaps for its metal 1 bitlines used in its 16 nm NAND flash as shown in figure 9. The opportunities for continued lithographic shrinking of planar NAND flash seem limited as immersion lithography with quadruple patterning may only get to the low 1X nm node, and air gaps are already being extensively used to suppress cell-tocell interferences. The gate wrap around structures used by Samsung, Hynix and Toshiba may scale to about 10 nm and Micron’s planar floating gate might get them to sub-10 nm geometries. But in the end, NAND flash will go vertical. And here, Samsung was first off the mark with the release of their 3D V-NAND flash in the summer of 2014. Fig. 7: Toshiba 15 nm NAND floating gate air gaps (Source: TechInsights) Fig. 8: Samsung 16 nm NAND floating gate air gaps (Source: TechInsights). Fig. 9: Micron 16 nm NAND bitline air gaps (Source: TechInsights). www.electronics-eetimes.com Electronic Engineering Times Europe July-August 2015 7


EETE JULAUG 2015
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