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EETE JUNE 2013

Sharing the costs of research to circumvent the economics’ barrier By Julien Happich Last month, imec’s technology forum which took place in Brussels put a clear emphasis on the synergies that should be leveraged from the many fields of research explored at its international campus and across its hundreds of partnerships. Several key industry players shared their views on what could come beyond the 10nm node, and although the roadmaps became foggier as they ventured further into the future, a recurring message was that no company alone could afford the kind of investments and risk-taking associated with leading-edge processes. Director of components research at Intel, Mike Mayberry’s was prompt to highlight the challenges associated with costly and wide-ranging research on multiple fronts in an era of consolidation that has fewer technology players. While the Semiconductor Research Corporation (SRC) had 34 members in 1998, only 13 members remain today, which implies fewer end customers of research and overall less options being explored, Mayberry noted. This means consortia need to adapt and join their forces to engage in research before choices are made on the next technology nodes. This way, companies can share the risk of long range research on multiple fronts, and also share the benefits when an optimum transistor Fig.1: Gate All Around (GAA) transistor architectures at Intel. Fig. 2: Spintronic devices built on multi-layered materials. technology is found. For Mayberry, the technology nodes up to 10nm are pretty much defined and under development, but what’s beyond the 10nm node remains blurry with some broad optimization choices to be made for transistors. You want to increase charge mobility for a better ON-state while increasing device confinement for a better OFF-state (and thus less leakage). Mobility could be increased with new materials including Ge, new II-V compounds, carbon nanotubes or graphene, while increased device confinement could be realised through innovative electrostatic structures, moving from bulk silicon channels to Ultra- Thin Body (UTB) Silicon-on-Insulator (SOI) to FinFETs (wrapping the gate around three sides) to wires or dot transistors with a Gate All Around (GAA) architecture as shown in figure 1. Though this latest implementation would be the limit to structural electrostatic control, according to Mayberry, noting that with nanowires 6nm in diameter and transistors fabricated at a 7nm pitch, you would lack the required number of dopant atoms to make the devices work in such reduced volumes. Manufacture apart, another issue is how to control these devices. “If you look ahead, beyond visibility on the roadmap, the road becomes foggy but you know it doesn’t necessarily end. Instead, there are inflection points” commented Mayberry. Hence, with voltage scaling limited by charge mobility and the size of devices being limited by their intrinsic electrical behaviour, spintronics could be the future. Spintronic circuits are not based on charges but on electrons’ spins, which define different magnetic domains within multi-layered materials. Charges and spins travel across the devices in different directions, such circuits use mixed domains. So beyond CMOS, various Noncharge devices are being developed theoretically, such as all spin logic (ASL), spin torque oscillators (STO), spin torque majority gates (STMG) or nanomagnetic logic (NML) to name a few. Intel has actually demonstrated a spin filter based on very fine magnetic layers – see figure 2. Presenting imec’s capabilities for CMOS scaling in the next 10 years, Aaron Thean, director of the logic R&D program hinted at IIIV/SiGe/Ge heterogeneous FinFETs – see figure 3 - for increased electrostatic confinement while improving charge mobility. Another issue is to manage process variability, which becomes increasingly limiting as devices shrink. Moving beyond FinFETs, imec is experimenting with vertical nanowire architectures and rod-shaped gate-around devices. Thean reckons that a 16% shrink can be achieved relative to 2-D layouts. The research centre has managed to grow direct self-assembled InAs vertical nanowire on silicon using sub-lithographic surface guides. It is also doing fundamental work with new 2-D flake materials, demonstrating electrical devices with molybdenum disulfide (MoS2) and tungsten di-selenide (WSe2). Gate-all-around (GA) structures are also a good candidate for 3-D memories according to Keyvan Esfarjani, vice president technology & manufacturing at Intel and co-CEO of IMFT (IM Flash Technologies, a joint venture between Intel and Micron Technologies). Esfarjani anticipates that memory cells could be arranged as 2-D arrays of vertical semiconductor channels across many levels of GA structures to form multiple volt- 16 Electronic Engineering Times Europe June 2013 www.electronics-eetimes.com


EETE JUNE 2013
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