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Fig. 7: Suggested printed-circuit layout for high voltage performance at an isoSPI interface. pair itself can be biased to “earth” potential with high value resistors to each line as shown in Figure 5. Since the capacitors are in series in this situation, at least 22nF is recommended (33nF/630V type shown). Links between daisy-chained LTC6804-1s on the same board do not need any capacitor couplings since the potential is ordinarily < 50V, usually requiring only a single transformer section as well ( see figure 6) since the noise ingress without a cable is far smaller. High voltage layout The printed circuit layout should include wide isolation spacing across the main dielectric barrier, namely, the capacitors. Figure 7 shows a placement example that provides good high voltage performance, with the blue regions representing frame ground (left side, with twisted-pair connector) and IC common (right side). Note that the transformers must withstand HV transient potentials, so clearance is maintained there as well by using a 1206 size-biasing resistor. The HF decoupling capacitor and impedance termination resistor can be small parts (0602 size depicted). Another good practice to avoid leakage current across the HV barrier is to suppress soldermask in the area of the HV components (parts over the “gap” between grounds). This facilitates effective rinsing of flux residue under the parts, and avoids moisture retention in the porous soldermask layer. Special considerations for an isoSPI bus The previous circuits apply to point-to-point isoSPI links, but one of the important cases for providing a high voltage solution is the bus-connected addressable LTC6804-2 with the twisted- ISO9001:2008 Fig. 4: Complete high voltage isoSPI point-to-point link. Fig. 5: High voltage daisy-chain isoSPI link with isolated wiring. Types with physically separated windings have poor pulse fidelity due to excessive leakage inductance. The units shown have a 50V DC continuous rating. Fig. 6: Daisy-chain isoSPI link for sameboard interconnections. Complete the picture Figure 4 shows the complete circuit when using the L-C solution with CMCs as the transformers. Since the usual isoSPI application includes beneficial CMC filtering sections (integrated in the case of standard LAN parts), this circuit includes a recommended discrete part to retain that function. The coupling capacitors are high quality 10nF–33nF parts with an 1812 footprint (630V or 1kV rating). Here, we assume that the LTC6820 is operating at chassis ground potential, so that biasing of the twisted pair is at a safe level. In situations where both ends of the pair are at floating potentials, as in links between daisy-chained LTC6804-1 modules, then capacitors can be used at both ends of the link and the www.norsun.com.tw For more information please contact gwenlin@norsun.com.tw directly www.electronics-eetimes.com Electronic Engineering Times Europe June 2014 49


EETE JUN 2014
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