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EETE MAR 2014

EDA SPECIAL Eight tips to accelerate SoC physical design at RTL By Francois Rémond The growing complexity of modern System on Chip (SoC), the design effort associated with the increasing pressure on silicon cost, and the pressure associated with shortened schedule requirements, makes it essential to use innovative implementation approaches to optimize silicon area and ensure a short and predictable timeline. Silicon design usually suffers from the disconnection of needs between logical designers and physical architectures. This disconnect leads to costly iteration loops to reconcile incompatible options taken by design teams working in isolation. In this article, we will review the essential points to consider in order to ensure a smooth transition between the logical and physical worlds. Logical and physical implementation context Let’s have a look at the situation. At the beginning of the design process, the SoC’s initial representation is captured based on the functional description of the circuit and the logical architecture suitable to achieve the functionality and performance. This is usually expressed as shown in figure 1. When it comes to physical implementation – with the assumption that flattening the entire design is not an option due to the size of modern SoCs and the limited capacity of place and route tools at deep submicron nodes – we have to determine a suitable hierarchy for the backend implementation to result in an optimal design. The traditional approach was to mimic, in the physical domain, the hierarchy inherited from the RTL coming from the logical assembly of the SoC – see figure 2a. The main drawbacks with this Fig. 1: A typical SoC today. approach are the huge complexity of the top-level floor plan, the overall synchronization of the sub block’s development and the final timing convergence. Recently, it became more common to harden some specific parts of the design, creating the adequate level of hierarchy in the RTL and flattening the remaining part of the SoC – see figure 2b. The benefit of this methodology is that it limits the complexity of the top-level floor plan. However, since the bus fabric is implemented at the top level, timing convergence remains a challenge, and the wire dominant nature of the bus potentially makes the silicon utilization less than optimal. To further improve the previous approach, a designer can choose not to have any logic at the top level of the circuit by pushing all the circuit components, including bus fabric, within the physical partitions leaving only inter-partition connections at top level – see figure 2c. The designer could alternately connect those physical partitions by abutment (inserting feedthroughs for the connections having to traverse a physical partition). This approach leads to an extremely optimized usage of the silicon (as the wire dominant nature of the bus is merged within blocks which are more gate intensive), along with a predictable timing closure, provided a number of good design practices have been followed. Looking at figure 2c, it is obvious that the physical hierarchy is not reflecting the functional hierarchy that was elaborated during the logical assembly of the SoC in figure 2a. Let’s investigate how to move from the logical to the physical domains. Tips for optimized SoC realization At the beginning of the implementation process, it is important to identify the degrees of freedom that exist: The IO ring (typically predefined) provides strong constraints to the placement of interface blocks, while the elements that primarily connect to the internal bus have more flexibility for their location within the die. After this step, a partitioning study must be started in order to define the proper grouping of IPs within physical partitions, at a stage where enough information is available (at pre-RTL stage, at RTL, or at netlist level) depending on tools available and desired precision. Balancing the physical partition area If at all possible, having physical partitions of similar size simplifies the top level floor plan along with the pin distribution at the partition border. Accommodating blocks of extremely different sizes often requires creating complex rectilinear shapes leading to a more congested routing. Minimizing top level routing Reducing the number of wires to be routed at top level (or using Francois Rémond is Solutions Architect at Atrenta www.atrenta.com 34 Electronic Engineering Times Europe March 2014 www.electronics-eetimes.com


EETE MAR 2014
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