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EETE MAR 2014 High-Performance, high reliable Power Supplies 15 W to 12 kW+ adapted to your challenging projects l AC/DC Power Supplies l Rectifiers and Battery Chargers l DC/DC Converters l Sine-Wave Inverters l Phase and Frequency Converters l AC- Input, DC-output UPS systems l Open Frame l Wall mount l 19” Cassettes l DC-input dimmable back-light inverters for LCD displays l Complete Power Systems in 19" and 23" Racks ABSOPULSE Marketing Europe GmbH PoBox 1501 8620 Wetzikon CH Tel. +41 78 896 50 49 Fax +41 44 944 38 44 Write us: See us: Follow-us on EETimes Europe feedthroughs) is a good design practice to make the top level more easily implementable. In order to achieve the target, cloning of specific logic blocks which generate many distributed wires across the die (like reset and DFT controllers, or some clock generators) will help. Minimizing high speed connections If the connections between physical partitions can be lowspeed connections, the final timing convergence will be easier. Clever IP grouping choices will help achieve this goal. Optimizing the clock distribution Enforcing “clock confinement” (i.e. having synchronous clock domains bounded inside a single physical partition, as opposed to an SoC-wide distribution of synchronous clock) is the best strategy along with minimizing high speed connections to ease the top level timing convergence. If properly achieved, along with reasonable timing budgeting at the physical partition border, it will allow confining the timing challenges within physical partitions (and then solving them locally). As a result, the final assembly of the SoC will not exhibit problems requiring reopening already timing clean partitions. Honoring power domains Multiplication of independent power domains (either standby area or DVFS domains) in circuits for the mobile market creates additional constraints to honor when defining the physical implementation strategy. Special care must be taken to ensure that different power domains will be properly isolated and that feedthrough signals (which can possibly cross power domain boundaries) will be buffered on the proper power supply. Optimizing the bus fabric architecture All the techniques listed above will drive the design team to rethink the bus fabric architecture according to the physical implementation needs. Doing this will allow the design team to match bandwidth and latency requirements and take each of the previous points into account during the final optimization of the bus design. Physically driven grouping of IPs has major implications on the bus architecture which cannot be anticipated at the early design stage. For a given class of traffic, permutations of IP connection slots will be done to allow the proper IP grouping to take place. And the timing optimization of the bus design (pipeline insertion) cannot be done before this final version of the bus being available. Verification of clock and power domain crossing A single clock domain crossing error can kill the functionality of the entire SoC, by introducing non deterministic flip-flop metastability behavior. This leads to random failures depend- Fig. 2: Different physical implementation strategies of the SoC. Electronic Engineering Times Europe March 2014 35

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