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EDA SPECIAL ing on PVT conditions which are extremely costly to debug at silicon level. This verification can’t be delayed until the final SoC assembly but needs to occur in a hierarchical way; it must be an intrinsic part of the handoff of the IP. Special care must be taken as the context of integration of an IP may change the clock relationships with respect to the original IP designer assumptions. All asychronism/synchronism assumptions have to be carefully reviewed. It is also important to eliminate synchronous connections between different power domains as those are almost impossible to close across the variety of possible voltage scenarios. Completeness of timing constraints The quality of the timing constraints that will be used to signoff the design is another key item to watch. The creation of the final SoC level SDC is a combination of a bottom up and top down approach. Timing exceptions are inherited from the IP, and clock constraints are propagated from the top of the SoC. Insuring the coherency between the various sets of SDCs is not a trivial task, especially when design is built from multiple sources (3rd party IPs, internal design reuse, new design blocks, etc ...) and the team is located on different continents (which is the case for most modern designs). Here, communication between the team members is the challenge. Those timing constraints have to be validated early in the design process for all modes of operation to drive the physical implementation. If properly budgeted at the border of each physical partition (and signed off at the partition level after implementation), then the final assembly and chip timing closure will not be a major challenge. Restructuring the design RTL We discussed the benefit of restructuring the design hierarchy to fit with optimized implementation. The question now is: at which stage of the design should this restructuring occur? There are two main reasons to restructure at the RTL: Benefit from RTL synthesis at physical partition level a) Propagating the input tie-up, tie-down, and floating outputs though the hierarchy will reduce the size of the netlist to implement. This reduction comes for free during the synthesis process, while it is more complex to implement at the netlist level where scanned flip-flops prevent this optimization to occur within a stitched scan chain. b) In-context synthesis with wire load models estimated from the predicted size of the physical partition will produce an “easier to implement” netlist with respect to timing criteria. c) Physically-aware DFT insertion (scan ordering and compressor insertion) will reduce congestion spots. The enabler for RTL restructuring to occur is the starting of high-level design floor planning and timing evaluation from the RTL representation. There are now reliable tools on the market to perform this task with adequate precision, in order to generate the directives for the RTL & SDC manipulation to happen. The sequence of operations is depicted in figure 3. To better control schedule predictability Starting this physical activity at the RTL is another way to discover early on (at a time where the RTL design may still be influenced), blocking points that could end up in long fixing iterations if discovered at the final stages of the design closure. This is called “prototyping.” A coarse grain synthesis followed by a fast placement generates a representation of the whole SoC which is used to evaluate congestion and timing issues early on, and determine corrective actions. It is the starting point of the partitioning activity we discussed above. The benefit here is to eliminate the loops from final timing analysis to RTL design, replacing them with local loops that are easier to control. The case study highlighted below shows the advantage of allocating time for “prototyping” the physical implementation of the whole SoC in advance (scenario 2 and 3 compared to scenario 1 in figure 4) along with the additional benefit of doing this prototyping at the RTL rather than at the netlist level (scenario 3 compared to scenario 2). Design complexity and market pressures make the die area and schedule control of modern SoCs important success criteria. It is therefore crucial to anticipate and validate critical design decisions as soon as possible. It is now possible to do this assessment at the RTL to bring more physical awareness within the RTL design phase to further optimize the silicon utilization and bring more controllability in the implementation process. Fig. 3: Moving from original RTL to restructured RTL. Fig. 4: Case study on prototyping benefits. 36 Electronic Engineering Times Europe March 2014 www.electronics-eetimes.com


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