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DDR4 PHY IP reaches 2667Mbps at 28nm: 3200Mbps next? Cadence Design Systems claims it has achieved 2667 Mbps performance on its double data rate fourth generation (DDR4) PHY Intellectual Property for 28nm, an industry’s best according to the EDA vendor. By providing both the DDR4 controller and the DDR4 PHY at that high speed, the company will allow designers to truly leverage DDR4 high-speed memories into servers, networking and consumer applications. “In 28nm, there has been no DDR4 IP in the market that we are aware that has achieved any more than 2400Mbps”, commented Andrea Huse, Senior Marketing Manager at Cadence Design Systems. “In general, IP for DDR3 has been in the 2133 Mbps range on the high side and we are currently planning DDR4 – 3200 IP using a smaller geometry node” she added. The DDR4 PHY IP will support higher densities than DDR3, but it has other significant advantages over DDR3, including greater reliability, better power efficiency operating from 1.2V instead of 1.5V for DDR3, higher capacity, explained the EDA vendor. Reliability, availability, and serviceability (RAS) are more robust since DDR4 supports command and address parity error detection and recovery, command blocking upon detection of parity error, but also a connectivity test mode. DDR4 also provides optional features like CRC protection for write data. Cadence www.cadence.com EDA tool verifies design rule check decks Sage Design Automation’ DRVerify is a new tool that verifies design rule check (DRC) decks. Used by process design kit (PDK) teams and DRC deck developers, DRVerify addresses the problem of DRC deck errors, especially in leading edge process nodes of 20nm and below. DRC deck errors that are found late in the design or after tapeout are very costly, and can cause yield issues, incur additional redesign and mask costs, and ultimately hinder the production schedule. Using the design rule definition as input, DRVerify generates an exhaustive set of tests that thoroughly checks the correctness and accuracy of the DRC code as it is being developed. New advanced semiconductor process technologies, at 20nm and lower, come with new design rules that are extremely complex. Implementing DRC checks for such rules is a laborious and error-prone manual programming task, and thus the resulting code can easily have errors and inaccuracies. CAD teams and designers try to create sets of layout test cases exhibiting both “pass” and “fail” conditions and use them to check the DRC deck. Today these tests are usually devised and made manually or assisted by scripts or layout design tools. DRVerify uses the iDRM formal graphical rule definition as its input, and generates test cases based on that input. It systematically searches all boundary conditions of the rule expression and creates every possible variation of the design rule expression that can change the check result. Using a sophisticated layout engine, DRVerify generates thousands of test cases per rule in a matter of minutes. In addition to verifying DRC decks, DRVerify is also used by design rule manual (DRM) teams to validate DRM design rule specifications. Sage Design Automation www.sage-da.com Optimized dataprep flow speeds up maskless lithography In a joint program, Aselta, a supplier of advanced data preparation software solutions, and Mapper Lithography, a supplier of electron-lithography equipment, have developed an optimized data preparation flow for geometries from 90 nm down to 14 nm nodes. The challenge of advanced multi-beam writers, especially at 20nm and below, is to find the optimal trade-off between wafer pattern fidelity which drives yield and writing time which ultimately drives cost. The solution for the Mapper’s writer is based on Aselta technology, Inscale, which correction algorithms provide a unique combination, allowing customers to reduce cost while augmenting quality. The software flow features a dedicated proximity effect correction, a simulation and analysis capability and a model-based verification engine fully interfaced with the oasis.mapper format. A complete FLX:1200 emulator has been implemented in order to mimic the pixelated data handling through the full data path. Simulation inside Inscale is achievable pixel-wise with a bitmap repartition identical to the final multi-beam exposure. On top, several software modules have been implemented like rasterization and dose mitigation. A new SmartBoundary scheme is adapted to Mapper’s data format to minimize alignment and stitching errors. Mapper Lithography www.mapperlithography.com Synopsys looks to hardware for faster ARC core designs Synopsys is moving to hardware to speed up software development on system-on-chip devices using its ARC cores. The ARC AXS101 and AXS102 SoftwareDevelopment Platforms are complete hardware and software platforms that include ARC processors, peripherals, pre-built Linux and MQX operating systems, device drivers, and application examples, enabling designers to start software development prior to SoC availability. They use an existing ASIC for the older EM cores and FPGA implementations for the newer HS34 and HS36 cores. Previously SoC designers had to use virtual models of the processor or wait until the chip design was taped out. Peripheral I/Os on the platforms include licensable Design- Ware Interface IP such as USB, Ethernet, UART, GPIO, SPI, I2C and Secure Digital (SD) and allow designers to use the same hardware and drivers in the final SoC implementation, reducing development effort. Additionally, the built-in HapsTrak connector on the ARC Software Development Platforms allows designers to quickly implement SoC prototypes using Synopsys’ industry-leading HAPS FPGA-based prototyping solution. Synopsys already has virtual models for the cores for SoC software designs. We provide models of our ARC processors where ARC nSIM is an Instruction Set Simulator intended mainly for software developers and ARC xCAM is a 100% Cycle-Accurate model mainly intended for SoC designers, said Allen Watson, Product Marketing Manager at Synopsys. Synopsys www.synopsys.com www.electronics-eetimes.com Electronic Engineering Times Europe March 2014 39


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