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computing AMD describes notebook processor Carrizo By Rick Merritt Advanced Micro Devices will describe at the International Solid-State Circuits Conference the engineering prowess behind its next-generation notebook processor. Carrizo packs 29% more transistors and squeezes double-digit gains in performance and drops in power consumption out of the same 28nm process and die area as its current Kaveri chip. AMD uses the extra space to pack its previously external south bridge I/O unit into the die, saving system level power. The company claims the chip is also the first x86 to provide hardware-assisted decode of the new High Efficiency Video Codec (H.265). The net result is a chip that will sport power and performance advantages for some mainstream notebooks over its competitor, Intel’s Broadwell made in a 14nm FinFET process that debuted at CES in January. However, Intel still commands a significant lead in CPU performance. In addition, the 12-35W Carrizo family requires a fan making it too hot and power hungry to find sockets in notebooks. The net accomplishment of Carrizo is impressive, but it’s unclear if the business impact will be adequate to assure healthy growth for the company led by its new chief executive, Lisa Su. AMD lost $330 million in its latest quarter and laid off 7% of its staff in October, a week after Su took over as CEO. Because “AMD’s integrated graphics core is quite powerful, better than any of Intel’s GPUs – Carrizo is the equivalent of a graphics card with a processor and south bridge for free,” said Tom Halfhill, senior analyst for market watcher The Linley Group. However, “everyone’s worried about AMD long term, though they are doing well in the custom videogame processor business, Lisa Su has a tough job ahead,” he added. The ISSCC paper will detail many of the chip’s advances packing its core into a smaller area and delivering power consumption savings, according to co-author Sam Naffziger, one of four AMD corporate fellows and the company’s lead engineer on power issues. “We’ve done a lot of work to squeeze at least a node’s worth of improvements out of the design -- It wasn’t easy but the opportunities were there,” said Naffziger. “If you look at transistors per millimeter, Broadwell is only 20% denser, so we are doing amazingly well at two technology nodes behind Intel, enabling HEVC and south bridge integration that it doesn’t have,” he said. “We will have an advantage in some cases and they will in others,” Naffziger added. “Our graphics are unparalleled and will continue to win there, but CPU is Intel’s forte --we have our plans to improve our CPU core but we will not close that gap today,” he said. Naffziger declined to comment on AMD’s plans for 20 or 16nm designs or to give an update on AMD’s road map for x86 and 64-bit ARM cores announced in May. He also declined to name the foundry where AMD will make Carrizo or give target frequency and price for the chip expected to be formally announced before July. However he did share details in the ISSCC paper about how AMD applied to Carrizo physical design techniques from its GPU cores. Their auto place-and-route methodology and high density libraries helped shrink the chips metal layer count from 13 to 9 tracks, shrinking wires and saving power. Other advances enable users to access all 8 GPU cores on the design. In its prior 17W Kaveri chip users could only access 6 of 8 graphics units. The chip also marks first full implementation of the AMD-led Heterogeneous System Architecture spec for letting GPUs and CPUs share coherent memory links. Carrizo supports graphics context switching, the only piece of the HSA 1.0 spec not in the prior Kaveri chip. The paper also describes a handful of power management techniques AMD applied in Carrizo. They include new techniques for mitigating voltage droop and use of 10 on-chip sensors monitoring frequencies across about 500 pathways. AMD’s new Excavator x86 core fits in 23% less area than the prior core, in part due to use of the company’s dense physical design methods and libraries for graphics cores. Methods for handling voltage droop reduced CPU power consumption 19%. 10 Electronic Engineering Times Europe March 2015 www.electronics-eetimes.com


EETE MAR 2015
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