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EETE MAR 2015 The end of clock frequency scaling prompted the genesis of multicore architecture. cess node developments, enabling Iridium and more importantly their customers benefit in terms of cost & form factor through innovative new architecture approaches, rather than process shrinks of the original ASSPs. In what are now mature process nodes, ASIC development times are shortened considerably due to the availability of semiconductor IP, production proven on those nodes. As the process node shrink cycle lengthens, typical Product Development cycle now outperforms the process node cycle in delivering price/performance improvements. Hardware optimization becomes relevant In the past there was little motivation to optimize hardware or architecture, when gains could be made by cramming more features into software, waiting for a semiconductor upgrade cycle and then it would start to run well as Moore’s Law delivered semiconductor performance. Remember how slow WinXP and Vista ran when they first came out? Megatrends like open compute projects, the maker movement, hardware hackathons, are all examples of (or reactions to) the realization that gains from product architecture optimization can and do outpace those of semiconductor upgrades. Conclusion In the post Moore’s law world, architecture matters, hardware optimisation matters, doing custom ASICs are not just feasible, but a necessary option for many System Companies and OEMs. As process technology nodes advance and Moore’s Law slows at the leading edge, falling costs and increasing capacity on more mature nodes, coupled with the availability of high performance RF and mixed-signal IP is enabling a new paradigm in hardware and product innovation. OEMs can now embark on custom ASIC developments to take advantage of higher levels of integration, realising significant BOM savings. While the open hardware movement, and open compute projects are still niche areas and for now custom ASICs are maybe out of reach, other megatrends like IoT are driving new platforms, architectures and opportunities. Not in over 30 years, have custom, mixed-signal, ASIC developments been within reach of so many lower volume hardware applications. This article first appeared on EE Times’ Planet Analog website. Electronic Engineering Times Europe March 2015 17 Newestproducts_93x277.indd 1 04/03/15 15:13

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