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DEBUGGING &PROGRAMING TOLS within a structure cannot be indexed without writing additional code, but this is not too difficult. The following code shows how to access nibbles in an array of structures: struct nibbles { unsigned n0 : 4; unsigned n1 : 4; unsigned n2 : 4; unsigned n3 : 4; } mydata100; unsigned get_nibble(struct nibbles words, unsigned index) { unsigned nibble; nibble = index % 4; index /= 4; switch (nibble) { case 0: return wordsindex.n0; case 1: return wordsindex.n1; case 2: return wordsindex.n2; case 3: return wordsindex.n3; } } A similar put_nibble() function would be required, of course. The other way to code a solution would be to perform all the bit shifting explicitly in the code, which is really just emulating what the compiler might generate. It is unlikely that a human programmer could produce code substantially more efficient than a modern compiler. Speed optimization. There is little a developer can do to improve speed of access to data beyond the optimization that the compiler does (i.e., not packing the data for fast access). But one option is to locate data in the fastest available memory. An embedded toolchain includes a linker, which will normally have the flexibility to effect this optimization. This opens up a few possibilities for consideration: The fastest place to keep data is in a CPU register, but these are in short supply and should be used sparingly. Most compilers make smart choices for register optimization. RAM is the fastest type of memory in most systems. Obviously, variables tend to be located in RAM, but it may be worthwhile to ensure that constant data is copied into RAM as well. This is commonly done automatically, as code is normally copied from flash to RAM for execution. Microcontrollers typically have on-chip RAM, which is faster than external memory. So ensuring that speed-critical data is located there makes sense. Memory is commonly cached into an internal buffer for fast access. Some CPUs permit locking of a cache so that the contents are always immediately available. Embedded software developers are always interested in the efficient use of resources. Careful coding and use of compiler optimizations can ensure that code is optimal for a given application. To complete the job, a similar approach must be taken to the handling of data, where the balance of memory footprint against access time needs careful consideration Telit adds ARM compiler to its App Zone Telit Wireless Solutions announced the availability of the ARM Compiler as an optional addition to the Telit AppZone, the integrated development environment for its popular GE910, HE910, UE910, UE866 and UL865 cellular modules. Following an agreement with ARM, Telit can now offer the ARM Compiler as an option for optimal performance and size management. For professional grade, real-time functionality, the optional ARM Compiler enables engineers to take full advantage of the module’s embedded processing capabilities. The toolchain incorporates a highly optimizing C/C++ compiler, assembler, linker and libraries for embedded software development. Telit AppZone is an integrated Application Development Environment which provides a full suite of development tools including everything one needs in order to start develop immediately. Telit Wireless Solutions www.telit.com Secure kernel hypervisor moves into ARM Both Lynx Software Technologies LynxOS 7.0 RTOS and its LynxSecure separation kernel hypervisor are moving to new ARM-based processors, allowing the development of military-grade security to protect ARM-based embedded designs for IoT. LynxOS 7.0 is being migrated initially to the ARM Cortex-A series of processor cores, including processors from Xilinx, TI and Freescale. LynxSecure is being migrated to Cortex-A family members that offer hardware virtualization support. The LynxOS 7.0 RTOS uses features such as access control lists, audit, quotas, local trusted path, account management, and OpenPAM. These capabilities mean that security can be designed into a connected embedded device rather than being added as an afterthought, and hence IoT edge and gateway devices can be deemed ‘secure by design’. The LynxSecure separation kernel hypervisor provides strict isolation on a single hardware platform, efficiently separates memory, CPU and devices without the need of a “helper” operating system that is commonly found in hypervisors. The virtualization technology in LynxSecure sits above the separation kernel, and by using hardware virtualization features found in many of the newest ARM cores, can provide performance very close to the native speeds for guest operating systems running in the isolated domains. LynxSecure can be used to securely separate different networks, for example IT and OT networks commonly found in IoT gateways, and it can securely partition persistent storage to isolate critical information from malicious threats. Lynx Software Technologies www.lynx.com 28 Electronic Engineering Times Europe March 2015 www.electronics-eetimes.com


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