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EETE MAR 2017

NEWS & TECHNOLOGY MEMORY Elucidating OxRRAM’s data retention shortcomings By Julien Happich In an attempt to better understand the mechanisms behind OxRRAM’s data retention shortcomings, researchers from imec have investigated the impact that programming (electrical pulses and their frequency) could have on the memory’s failure and identified a way to optimize the metal-oxide interface in such devices. A Distinguished Member of Technical Staff at imec, Gouri Sankar Kar published a paper titled “Towards improved data retention in OxRRAM memory devices” of which detailed results have been presented at the 2016 IEDM conference by imec PhD student Michael Chen. OxRRAM memory, a class of resistive random access memory (RRAM) devices, has already shown its potential for embedded Internet-of-Things devices. The technology is highly scalable, reliable and simple (Left) OxRRAM crossbar cell and (right) cross-sectional TEM image of the TiN/HfO2/Hf device to process, but so far, a poor understanding of the device’s data retention failure mechanisms hindered mass production. An RRAM device in general relies on the formation of a conductive filament in a thin dielectric layer that is sandwiched between two electrodes. When an electric field is applied, the ionic movements and structural changes in this insulating medium cause a measurable change of the device resistance. Memory operation makes use of two different resistance states: high resistance state (HRS) and low resistance state (LRS). Switching from one to the other can be done by applying an appropriate electric field. The operation which changes the resistance for HRS to LRS is called a ‘set’ process, while the opposite is defined as ‘reset’. The specific resistance state (HRS or LRS) can be retained after the electric field is switched off, and this indicates the non-volatile nature of the RRAM memory. Now, in the OxRRAM-type of memory, the filamentary switching is based on oxygen vacancy migration in transition metal oxides. The technology shows excellent scalability and reliability, and can be fabricated by using a simple integration flow. Though, in low-current and fast-pulse programming regimes, a small population of fast-erasing bits (also called retention tails) typically appears. Imec previously associated these retention tails to excess mobile oxygen ions. During set/reset cycling, these oxygen ions can be injected in or removed from the conductive filament. When the set pulse is insufficient to remove these excess ions from the filament, the ions recombine with oxygen vacancies, and this results in retention failure. The imec researchers have now extended this analysis by studying the impact of the program history on the data retention properties of the tail bits. Conventional assessment methods are performed on a device-by-device-basis, assuming that retention failures due to fast erasing bits are related to device-todevice differences – arising from e.g. variation in the processing of the memory device. In this novel research, the scientists assumed that the origin of the excess ions was related to inherent variations in the cycle-to-cycle set/reset programming. Therefore, to assess retention, a single OxRRAM cell (instead of an array of cells) was being programmed (set), sampled, and reprogrammed (reset) at retention baking temperatures, and this cycle was repeated over 1500 times (single cell cycle-to-cycle retention technique). The lead author and his team fabricated OxRRAM crossbar cells on top of a transistor in a so-called 1-transistor-1-resistor (1T1R) configuration, sandwiching a 5nm thick HfO2 layer (the dielectric) between a 30nm TiN bottom electrode and a Hf (10nm)/TiN top electrode. Measuring 40x40nm, the whole TiN/ HfO2/Hf stack was used to evaluate the impact of programming conditions. Different stacks were fabricated to investigate material engineering solutions, such as the role of the oxide-metal interface. And what the researchers found for the first time, was that the retention in the LRS state is largely dependent on the program history of the memory cell. For example, the use of a short reset pulse of high amplitude in combination with a long set pulse can largely improve LRS retention. They also showed that it is possible to clean excess O-ions by iterating short set/reset cycles. Also, the delay time between set and reset pulses plays an important role. When set programming is applied immediately after reset, worse retention is obtained compared to cases with some delay. In practice, this means that smart writing algorithms will be needed to avoid writing the same bit repetitively in a short time. For the HRS in a HfO2/Hf stack, experiments suggest that HRS retention failure is not governed by the concentration of remaining O-ions in the conductive filament. The results have been supported by modelling. The experiments were based on an earlier presumption that the retention strongly depends on the oxygen chemical potential profile (more specifically, the asymmetry of the profile) along the conductive filament, and additional experiments proved it to be true. An OxRRAM stack was made in which the Hf electrode was replaced with a Ti cap, exhibiting a worse chemical profile asymmetry. It was shown that Ti capping indeed gives worse data retention. These experimental and modelling efforts enabled the researchers to come up with an optimized OxRRAM stack, based on a TaOx/Ta system with ideal chemical potential profile. The new stack, in combination with an optimized programming sequence, shows much better data retention compared to the HfOx-based OxRRAM cell, for both the LRS and HRS states. The results were confirmed by conventional deviceto device retention tests. The new cell is also compatible with back-end-of-line thermal stress. 10 Electronic Engineering Times Europe March 2017 www.electronics-eetimes.com


EETE MAR 2017
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