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AUTOMOTIVE ELECTRONICS Fig. 2: Camera to processor connection. camera to a processor for analysis and to a display for viewing. In systems like these, the MIPI Camera Serial Interface (CSI) provides a protocol framework to pass data from the camera to the processor. The actual transmission is accomplished by using another MIPI specification, MIPI D-PHY, which is a physical layer transceiver specification. Using MIPI D-PHY means that the interface will operate at the lowest power and deploy at a minimal cost. MIPI Alliance develops specifications with flexible architectural definitions, recognizing that targeted implementations are necessary to realize an optimal combination of physical pins and transfer rates. Figure 2 is one example of a targeted implementation; a simplified diagram of the camera-to-processor connection. The camera sub-assembly has the camera sensor and supporting circuitry for image capture and for organizing the image data for transmission using a D-PHY Tx macro. The camera image is serialized and sent across to an Image Signal Processing sub-assembly containing the supporting circuitry for receiving the data – a D-PHY Rx macro. The physical connection between the Tx and Rx side is made using a MIPI interface. NXP designed such a system using the MIPI CSI-2 specification and a D-PHY hard macro provided by Mixel. Mixel’s MIPI D-PHY in NXP’s S32V234 The NXP design that utilizes the MIPI interface is called the S32V234, as shown in figure 3 (see upper left-hand corner). The S32V is an ADAS solution for vision, sensor fusion and surround view applications. It features a quad-core ARM Cortex- A53 processor, the NXP APEX Image Cognition Processor, Vivante GC3000 Processing Unit, and an advanced memory bus system architecture. The system is designed to interface with a variety of image sensors, like the Sony IMX224. That sensor has a MIPI CSI-2 interface for linking the sensor to a system-level chip like the SV32. The MIPI CSI-2 interfaces have a maximum output data rate of 1.5 Gbps/lane, and the number of output channels can be selected from 1ch, 2ch or 4ch (lanes). A key part of this system is the transfer of the raw image data to the SV32 built-in image signal processor (ISP) with low or zero latency. The raw data is the processed efficiently using an advanced high performance SRAM system that compliments the tradition DDR memory management making the image processing in real time. The raw data transfer from the Camera to the S32V is accomplished via a MIPI CSI-2, D-PHY interface and received by the Rx D-PHY hard macro. The data is serialized and transferred at a high speed to allow flicker free processing. Mixel provided the D-PHY IP Rx+ hard macro for the NXP design. This macro is optimized as a receive-side custom implementation that efficiently fronts the CSI-2 interface in the system-level chip, S32V. It’s noteworthy that the MIPI D-PHY specification defines a universal form of the D-PHY with symmetrical Tx and Rx capabilities. Fig. 3: S32V234 ADAS processor block diagram. It’s easier when all you need is in onEev epryltahicnge F.PGA. Everything FPGA. www.electronics-eetimes.com Electronic Engineering Times Europe March 2017 35


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