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EETE MAY 2013

TSMC starts FinFETs in 2013, tries EUV at 10 nm By Rick Merritt Facing heated competition from Globalfoundries and Samsung, TSMC pulled in plans for initial production of its 16-nm FinFET process to the end of 2013. In addition, it hopes to adopt extreme ultraviolet lithography to make 10-nm chips starting in late 2015 but is still researching e-beam as an alternative. Company executives detailed the new processes and how they aim to get there at an annual symposium here. They also provided an update on their work on 3-D chip stacks and their ongoing ramp of today’s 28-nm process node. “It looks like we have another 7 to 8 years ahead in advances -- maybe more -- we can see in technology down to 10 and even 7 nm,” said Morris Chang, founder and chief executive of TSMC, speaking to a small group of press after a keynote here. “Moore’s Law is going to go on and we will be there -- if anyone pursues it, we will pursue it,” he told an audience of several hundred chip designers. Chang, a veteran of more than 50 years in semiconductors, forecasts four percent growth for the industry this year. “Fabless companies probably can enjoy nine percent growth this year, and we are also optimistic about ourselves -- we expect growth in the teens,” he said. He said TSMC will spend more than $9 billion in capex in 2013. That’s up from $2 billion in 2009. A heady ramp for 28 nm Much of this year’s growth comes in the 28nm node. Just a year ago, Qualcomm’s chief executive Paul Jacobs was telling his investors the company could sell more of the advanced chips than it could make at TSMC and was searching for capacity elsewhere. In June 2010, TSMC broke ground on a so-called Gigafab 15 site in Taichung, Taiwan, it planned as its manufacturing center for 28-nm chips. By April 2012, just 22 months later, it started production in half the planned facility -- a record for the Taiwan foundry. Within eight months it was kicking out 50,000 28-nm wafers a month -- another record -- but it still wasn’t enough. So, next month the second half of the facility is set to produce its first wafers and within five months is expected to beat the old record and add another 50,000 28-nm wafers/ month. “The scale is difficult to appreciate,” said Chang. The “unprecedented ramp of 28-nm chips came TSMC now starts three new fabs each year. with an acceleration in time to good yields and volume production,” said J.K Wang who oversees TSMC’s 300-mm fabs. The foundry expects to see even faster ramps at 20 and 16 nm, so it has several thousand engineers preparing for those nodes at its fab 12 and 14 facilities today. “In the past, we built one phase of a new fab each a year, now we typically initiate three phases a year,” said Wang. The foundry estimates it makes 1.3 million logic wafers per month total now, far ahead of Samsung in second place at about 900,000 logic wafers/month. It estimates it will produce a whopping 13.5 million wafers/month in 2017 if it continues its growth. Next up—the 20-nm node Some industry watchers say 20 nm will be an interim node to work out the wrinkles in double patterning lithography, but not offering many advantages to chip designers. Don’t tell that to Jack Sun, chief technology officer of TSMC. By 2017 he predicts the Taiwan foundry will be making as many 20-nm chips as it 28-nm ones. He claims the node will offer a 1.9x increase in gate-level density over the high-performance 28-nm node, although some speculate rival Globalfoundries will only deliver a 16 percent density increase at 20 nm. Sun also said 20-nm chips could sport 20 percent higher speeds or 30 percent less power consumption than 28-nm ones. That’s significant though not as much as traditional full nodes. The 16-nm node that follows it will have similar characteristics, but a future 10-nm node will have slightly greater benefits, he said. TSMC expects to have about 20 tapeouts at the 20-nm node this year at its fab 12 and 14 plants. Mass production at that node really starts in 2014, said Wang. Designs using an 80 to 90-nm pitch can be designed using single patterning. But more fine lines will require a second pass under the immersion lithography scanner. The ecosystem is ready, said Cliff Hou, vice president of R&D at TSMC. Some 38 features of 28 EDA tools have been tested for 20 nm, 185 design kits are available for the node and both foundation and critical interface IP blocks have been verified, he said. TSMC expects silicon back in May on a 20-nm test device based on an ARM Cortex A15 core, Hou said. “Moore’s Law has another 7-8 years ahead, said TSMC founder Morris Chang” 12 Electronic Engineering Times Europe May 2013 www.electronics-eetimes.com


EETE MAY 2013
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