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Faster path than expected to FinFETs TSMC surprised Silicon Valley announcing it will produce its first 16-nm wafers with FinFETs by the end of the year. That matches the timetable Globalfoundries and Samsung announced here just weeks ago. In general, the industry plans to take what it learned about making 20-nm chips with double immersion lithography and graph 3-D transistor structures on to it. Thus the move makes advances that are less than a full node in density, power and performance. “We are confident the 16 FinFET process will be there for prime time production next year,” said Sun. TSMC showed a chart estimating a 64-bit ARM core in the 16-nm node will have 90 percent greater performance than a 32-bit ARM A9 core in 28 nm. By contrast an ARM A15 in the 20-nm node will give about a 40 percent boost, TSMC estimated. Current tests of the 16nm process using a 128 Mbit SRAM are yielding “ahead of plan,” said Sun. The core runs at 0.8V and the I/O at 1.8V, he added. Foundational IP such as standard cells and memory cells are ready for the node. However, the first critical interface blocks won’t start testing until June, said Hou. A look into the foggy 10nm future By the end of 2015, TSMC hopes to start shipping its first 10nm wafers using EUV lithography. The key word is “hopes.” Throughput of EUV machines need to get well beyond “100 wafers and hour or it will not be cost effective,” Sun told EE Times. TSMC has been working with an NXE3100 EUV scanner and has demonstrated using it to make fins in a single pass. It hopes to get an NXE3300 soon. Hedging its bets, TSMC is pioneering multiple e-beam techniques that are “showing good progress,” Sun said. It is using parallel beams to increase throughput which is still too slow, but “prototype tools shows promise that in the future the cost of ownership could be less than EUV,” he added. Even if EUV hits its targets, the 10nm node also requires The 20-nm node will be as big as the 28nm node by 2017, Sun predicts. use of self-aligning techniques with immersion lithography to minimize the need for EUV to just some critical layers. TSMC also is developing a so-called G-rule that automates the tricky process of handling color conflicts in double patterning. If all goes well, the 10nm node could offer another 90 percent increase in gate level density. It could also deliver 35 percent speed ups at the same power or 40 percent in power savings at the same speed as a 16nm device, Sun estimated. 3-D stacks and 450-mm wafers The good news in 3-D stacking is TSMC is now hitting better than 95 percent yields for the kinds of 2.5-D silicon interposer designs Xilinx pioneered with four FPGAs laid next to each other on a silicon interposer. The foundry expects multiple tapeouts All three top foundries now expect to ship FinFETs in 2014. of such devices this year. “This is the low hanging fruit and a natural start in 3-D,” said Sun, noting the interposers will scale from 100 to 50 microns. It’s still early days for true 3-D vertical stacks using through silicon vias. The TSVs are scaling from six to two microns and various prototypes are in the works. Last year, TSMC tried a 2.5-D stack that set 40-nm logic and a Wide I/O memory die from SK Hynix next to each other. The Wide I/O die passed tests to comply with the Jedec spec, but more tests are still in the works. In May, TSMC hopes to tapeout a “true 3-D IC stack” at 28 nm using all memory chips, Hou said. Later it will try merging logic and memory in a vertical stack with TSVs. Sun predicts such chips might be ready for production in 2015 or 2016, matching recent estimates from Globalfoundries. Meanwhile more logic 2.5-D stacks will ship this year and mixed logic with memory 2.5-D stacks should emerge in 2014, he said. “In the not too distant future there could be a silicon superchip smartphone with a 3-D package,” Sun said. The next generation of silicon wafers is further out -- not coming online until at least 2016, said Wang. TSMC is acting as general contractor for the G450 Consortium fab that is now testing prototype tools for 450-mm wafers. TSMC estimates all the tools will be ready for high-volume production by the end of 2015 - except the litho systems. Immersion systems won’t be ready for 450-mm wafers until late 2017, and EUV…well, Wang hopes they could be ready at the start of 2018. Again the key word is “hopes.” So, TSMC plans to start a pilot 450-mm wafer line in 2016 or 2017, ramping production of 10 or 7-nm chips. A 450mm and a 300mm wafer compared. www.electronics-eetimes.com Electronic Engineering Times Europe May 2013 13


EETE MAY 2013
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