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EETE MAY 2013

Texas Instruments aims to develop a better way to the cloud with HP Project Moonshot By Paul Buckley Texas Instruments Incorporated is participating in HP Project Moonshot and the HP Pathfinder Innovation Ecosystem and has affirmed the company’s commitment to helping HP develop innovative, energy-efficient server technology optimized to address new styles of IT workloads. TI’s KeyStone I-based multicore System-on-Chips (SoCs), now shipping, further advance efforts to design, deliver, standardize and deploy innovative solutions that are tuned for today’s extreme-scale demands. HP Project Moonshot, a multi-year, multi-phased program, is dedicated to the development of a new family of softwaredefined servers, including extreme low-energy processing technology purposefully built to address surging infrastructure pressures from emerging application trends. Pioneering the future of extreme-scale technology, the HP Moonshot System is the first solution with a modern architecture engineered for the new style of IT, utilizing a revolutionary server designed to help customers significantly reduce physical space requirements, energy use and costs. The close collaboration between TI and HP over the last year ensures that TI’s SoCs are the right fit for the HP Moonshot System. TI’s KeyStone II-based SoCs, which integrate fixed-and floating-point TMS320C66x digital signal processor (DSP) cores with multiple ARM Cortex-A15 MPCore processors, packet processing, security processing and Ethernet switching, give customers the performance, scalability and programmability needed for a variety of applications in the high performance compute, cloud computing and communications infrastructure markets. These new SoCs offer customers more than four times the capacity and performance at the same power relative to existing solutions*. This is due, in part, to the C-programmable floating point C66x DSP cores that bring about a tremendous amount of compute performance at low power. These SoCs are best-inclass in terms of performance and power efficiency due to their all-in-one nature and functionality. The KeyStone architecture claims to be the industry’s first implementation of quad ARM Cortex-A15 MPCore processors in infrastructure-class embedded SoC, offering developers high capacity and performance at reduced power for networking, high performance computing. The architecture provides an unmatched combination of Cortex-A15 processors, C66x DSPs, packet processing, security processing and Ethernet switching, transforming the realtime cloud into an optimized high performance, power efficient processing platform. The KeyStone architecture 20 plus software compatible devices across KeyStone I and KeyStone I generations, enabling customers to more easily design integrated, power and costefficient products for high-performance markets from a range of devices. To help advance HP Moonshot, the expanded HP Pathfinder Innovation Ecosystem establishes a close collaboration of industry-leading technology partners dedicated to accelerating the development and deployment of energy-efficient, workload optimized servers. New standard tracks soft IP usage through the semiconductor design By Julien Happich Accelera Systems Initiative has completed its IP Tagging 1.0 standard, designed to provide a mechanism to track critical soft IP data throughout the entire chip design and development process such that it can be readily identified, tagged, and used again for future designs. Using the Soft IP Tagging 1.0 standard, engineers now have the ability to easily determine if a block of IP is contained within a chip, if it is the correct version, and if it is a candidate for reuse. In addition, semiconductor foundries, providers of IP, and manufacturers of design tools now have a standard way to track IP usage and royalty information with their customers. The chip design process can include editing, synthesis, timing, placement, wiring, and other steps. Normally, control of a third-party IP source is lost once the block of IP is licensed, unlocked, or otherwise made available in clear code. IP Tagging 1.0 facilitates a data-driven method to tag a block of IP and track “where used” for applications such as ownership, royalty calculations, and recognition. It also facilitates the implementation of version identification for applicable bug fixes and errata and allows tracking of other data. “I would like to thank the members of the IP Tagging Working Group for their dedicated efforts in achieving this IP standard,” said Kathy Werner, Accellera’s IP Tagging working group chair. “Soft IP Tagging 1.0 not only provides a mechanism for version control and bug tracking, but can be used to determine the compatibility of an IP block for reuse in a future design. Engineers can now feel confident there is a standard methodology built around IP reuse, tracking, and data control.” The Soft IP Tagging 1.0 standard is available immediately for download under open source license at www.accellera.org 14 Electronic Engineering Times Europe May 2013 www.electronics-eetimes.com


EETE MAY 2013
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