Page 22

EETE MAY 2014

What exactly is DC power integrity? By Benjamin Jordan When I first learned to design digital electronics and layout a PCB, I was taught to put all the 74-series chips and the microprocessor in neat rows, and the rule of thumb was to add a single 0.1μF ceramic capacitor for decoupling to each device, and sometimes adding an additional 1μF tantalum or electrolytic for the micros in parallel. I never worried too much about getting power to each device - using a 20 or 30 mil trace was enough for a chip that never drew more than 100mA, along with the classic interdigitated +5V/GND “grid”. Of course, power electronic designs are a whole different ball game. And I always took a lot more time, care and planning with power supply and amplifier designs - making sure to use proper (star) grounding and keeping high-current loops as tight as possible. Some of this was more than 20 years ago now, and of course there has been a lot of development in the decoupling and power network topic since then. More elaborate and carefully placed decoupling schemes have to be designed for each new silicon process node, each new chip package generation and for each new PCB design as they become more densely packed with parts than ever. It’s getting difficult to find room for all the “rule of thumb” decoupling caps! And with BGA packaged devices down to 0.4mm pitch, that meanwhile draw several amps of current during use, it’s getting really difficult to plan and design a good power network on the PCB. Whether we like it or not, Power Integrity is a challenge that all PCB designers and engineers have to address. Power Integrity is talked about a lot these days. But a lot of the talk is really on the signal integrity side - I call it AC power integrity, which is really about the impedances of the power network at high frequencies. This deals with how the decoupling is designed as well as return paths for high-speed signals. While it is non-trivial, I don’t want to simply regurgitate this already very commonly discussed topic. I want to get down to DC… why? Well, it just seems to me that learning to walk before trying to run is a good idea. So let’s talk DC Power Integrity. At face value, it seems to be a simple enough topic - you just need to make sure there’s enough copper to get the necessary current to each device on the board. But that’s just at face value. When you start to work with fine-pitch device packages, manufacturing constraints and power requirements of said devices are almost completely at odds. Not only is it difficult to get the current needed to all the power pins, but you are also POWER design working with multiple supply voltages. This means that unless you want a high-layer-count PCB, you are going to have to get power to your devices through various split planes, and that’s just where the trouble begins. But before I go too far down into the rabbit hole of designing the power distribution networks, how can you tell if you even have a power integrity problem? Power Integrity issues are sneaky little blighters. Like cockroaches that rapidly scamper into the crevices when the light turns on - the moment you try looking for these issues is the moment they can’t easily be reproduced. But you may have a power integrity issue if any of the following symptoms occur to your assemblies: The CPU is resetting unexpectedly, or when a high-utilization thread enters execution. Memory devices keep failing content retention / corruption tests. Analogue front-end circuits are randomly inaccurate or out of design specs. CPU or FPGA devices fail catastrophically. FPGA configurations are corrupted during power up. PCB Vias go open-circuit after a period of use cycles or maybe even at first power on. Production PCBs suffer blistering in the common locations. PCBs suffer delamination in common locations. Trace or polygon neckdowns are fusing. Discoloration of laminate or solder mask material in some regions of the PCB. These symptoms fall into two broad categories of DC Power Integrity problems. For example, items 1 through 5 are the more sinister misbehaviours caused by transient voltage drops across the board. Sometimes they can be fixed with better decoupling but when talking DC, really more copper will improve the design. Items 6 through 10 are more serious power integrity issues where current density regularly exceeds the safe limits for temperature rise and the board is suffering from localized heating, or copper is outright fusing. There are some useful tools for avoiding these sorts of problems before prototype; for example the IPC-2152 conductor sizing charts. I would say it’s a must that every design begins with these charts as the basis for power network design rules for the PCB layout. However, there are designs that now approach a part density that make it necessary to design “on the edge” and work with means and duty cycles to make sure the board doesn’t fail. So, DC Power Integrity is the concern over making sure that each device in the design gets the power it needs, without suffering the problems mentioned, all while ensuring a reliable power network on the PCB. Benjamin Jordan is Sr. Manager for Content Marketing Strategy at Altium - www.altium.com 22 Electronic Engineering Times Europe May 2014 www.electronics-eetimes.com


EETE MAY 2014
To see the actual publication please follow the link above