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EETE MAY 2014

Measuring angular position and velocity By Jakub Szymczak resolvers use the magnetic coupling between primary and secondary windings to measure the precise angular position of a rotating element. Used in industrial motor controls, servos, robotics, power train units in hybrid- and full-electric vehicles, and many other applications, resolvers can withstand severe conditions, making them the perfect choice for military systems in harsh environments. Standard resolvers have a primary winding on the rotor and two secondary windings on the stator. Variable reluctance resolvers have all windings on the stator, but the saliency (exposed poles) of the rotor causes a sinusoidal variation in the secondary with the angular position. Figure 1 shows classical and variable reluctance resolvers. When the primary winding is excited with a sinusoid (Equation Fig. 1: Classical resolver vs. variable reluctance resolver. 1), a signal is induced in the secondary windings. The amount of coupling is a function of the position of the rotor relative to that of the stator, and an attenuation factor known as the resolver transformation ratio. Because the secondary windings are displaced mechanically by 90°, the two output sinusoidal signals are phase shifted by 90°. The relationships between the resolver input and output voltages are shown by the sine signal (Equation 2) and cosine signal (Equation 3). (1) (2) (3) where: θ is the shaft angle, ω is the excitation signal frequency, E0 is the excitation signal amplitude, and T is the resolver transformation ratio. Resolver-to-Digital converter The primary winding is excited with a sinusoidal reference. Two differential output signals, sine and cosine, are electromagnetically induced on the secondary windings. A resolver-to-digital converter (RDC) decodes the angular position and rotation speed of the motor shaft. A majority of RDCs use a Type-II tracking loop to calculate position and velocity. Type-II loops use a second-order filter to ensure that steady-state errors are zero for stationary or constant velocity input signals. The RDC simultaneously samples both input signals to provide digitized data to the tracking loop. An example of an RDC that uses this type of loop is ADI’s AD2S1210 complete 10-bit to 16-bit tracking converter, whose on-chip programmable sinusoidal oscillator provides the excitation signal for the primary winding. Typical resolvers require a low-impedance 3-V rms to 7-V rms signal to drive the primary winding. Operating on a 5-V supply, the RDC typically delivers a 7.2-V p-p differential signal on the excitation outputs. This signal does not have sufficient amplitude and drive capability to meet the resolver’s input specifications. In addition, resolvers attenuate signals by up to 5×, so the resolver output amplitude does not meet the RDC’s input amplitude requirements. A differential amplifier boosts the signal to the primary and improves signal-to-noise ratio. The output sine and cosine signals can then be attenuated with resistor dividers or a lowpass filter. Figure 2 shows a typical resolver-to-digital converter interface including amplifier and filter. Error sources The system accuracy is determined by the RDC, resolver, excitation buffer, input circuitry, and cabling. The most common sources of system error are amplitude mismatch, signal phase shift, offsets, and acceleration. Amplitude mismatch is the difference in peak-to-peak amplitudes of the sine and cosine signals at 0° and 180° for cosine, 90° and 270° for sine. Mismatch can be introduced by variation in the resolver windings, or by the gain between the resolver and the RDC’s sine and cosine inputs. The amplitude mismatch error oscillates at twice the rate of rotation, with a maximum of δ/2 at odd integer multiples of 45°, and no error at 0°, 90°, 180°, and 270°. With a 12-bit RDC, 0.3% amplitude mismatch will result in approximately 1 LSB of error. The RDC accepts differential sine and cosine signals from the resolver. The resolver removes any dc component from the carrier, so a VREF/2 dc bias must be added to ensure that the resolver output signals are in the correct operating range for the RDC. Any dc offset between SIN and SINLO inputs or COS and COSLO inputs will introduce additional system error. Jakub Szymczak is an applications engineer in the Precision Converters Group in Limerick, Ireland. He can be reached at jakub.szymczak@analog.com Fig. 2: Typical resolver system block diagram. www.electronics-eetimes.com Electronic Engineering Times Europe May 2014 37


EETE MAY 2014
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