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EETE MAY 2014

DIGITAL SIGNAL PROCESSING Fig. 3: Synthetic reference. The error introduced by the common-mode offset is worse in the quadrants where the sine and cosine signals are in antiphase to each other, which occurs from 90° to 180° and 270° to 360°. Another source of error is differential phase shift between the resolver’s sine and cosine signals. Some differential phase shift will be present on all resolvers as a result of coupling. A small residual voltage or quadrature voltage indicates a small differential phase shift. Additional phase shift can be introduced if the sine and cosine signal lines have unequal cable lengths or drive different loads. Most resolvers also introduce phase shift between the excitation signal and the sine and cosine signals. This error can be minimized by choosing a resolver with a small residual voltage, ensuring that sine and cosine signals are handled identically, and by removing the reference phase shift. Under static conditions, phase shift between the excitation reference and the signal lines will not affect the converter’s accuracy, but moving resolvers generate speed voltages due to the reactive components of the rotor impedance and the signals of interest. Speed voltages are in quadrature to the signal of interest. Their maximum amplitude is (4) In practical resolvers, rotor windings include both reactive and resistive components. The resistive component produces a nonzero phase shift in the reference excitation that is present when the rotor is both moving and static. Together with the speed voltages, the nonzero phase shift of the excitation produces a tracking error. To compensate for the phase error between the resolver reference excitation and sine/cosine signals, the AD2S1210 uses the internally filtered sine and cosine signals to synthesize an internal reference signal in phase with the reference frequency carrier. Generated by determining the zero crossing of either the sine or cosine (whichever is larger, to improve phase accuracy) and evaluating the phase of the resolver reference excitation, it reduces the phase shift between the refer¬ence and sine/cosine inputs to less than 10°, and operates for phase shifts of ±44°. Figure 3 shows a block diagram of the synthetic reference. The advantage of Type-II tracking loops over Type-I loops is that no positional error occurs at constant velocity. Even in a perfectly balanced system, however, acceleration will create an error term. The amount of error due to acceleration is determined by the control-loop response. Figure 4 shows the loop response for the AD2S1210. Input filter For best system accuracy, connect the resolver outputs directly to the SIN, COS, SINLO, and COSLO pins. This is not always Fig. 4: AD2S1210 loop response. feasible, however, as attenuation may be required to match the resolver’s sine and cosine signals to the RDC’s input, signal filtering may be required due to the noisy environment, and ESD or short circuit protection may be required at the resolver connector. Figure 5 shows a typical interface between the resolver and the AD2S1210. The series resistors and the diodes provide adequate protection to reduce the energy of external events such as ESD or shorts to supply or ground. These resistors and the capacitor implement a low-pass filter that reduces highfrequency noise coupled onto the resolver inputs as a result of driving the motor. It may be necessary to attenuate the sine and cosine signals to align with the input specification, by adding resistor RA. The AD2S1210 has internal circuitry to bias the SIN, SINLO, COS, and COSLO to VREF/2. This weak bias can be easily overdriven by including 47 kΩ resistors to bias the signals to 2.5 V. Excitation buffer A buffer is typically required to drive the resolver’s low impendence inputs. The high-current driver shown in Figure 6 uses the AD8397 high-current dual op amp with rail-to-rail outputs to amplify and level shift the reference oscillator output, optimizing the interface to the resolver. The AD8397 achieves low distortion, high output current, and wide dynamic range, making it ideal for use with resolvers. With 310-mA current capability for 32-Ω loads, it can deliver the required power to a resolver without the use of the conventional push-pull stage, simplifying the driver circuit and reducing power consumption. A duplicate circuit provides a fully differential signal to drive the primary winding. The output amplitude is set by the amplifier gain, R2/R1, and the common-mode voltage is set by R3 and R4. Capacitor C1 and resistor R2 form a low-pass filter to minimize noise on the EXC and (EXC) outputs. The capacitor should be chosen to minimize phase shift of the carrier. The total phase shift between the excitation output and the sine and cosine inputs should not exceed the phase-lock range of the RDC. The capacitor is Fig. 5: Interface circuit. 38 Electronic Engineering Times Europe May 2014 www.electronics-eetimes.com


EETE MAY 2014
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