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EETE MAY 2015

A printed WORM memory bank with 26 bits (1mm pitch) with contact electrodes and a common electrode. The bit size is approximately 0.2x0.3mm. “For bigger memories with a need to limit the number of electrical contacts using a two-dimensional matrix structure of the bits, one would need to implement a diode in series with each bit or utilize a more elaborated readout electronics to cancel cross talk between the bits”, clarified Ari Alastalo, Principal Scientist at VTT in charge of printed and hybrid functionalities, printed sensors and electronic devices. “In fact, the reading voltage is not limited by the WORM but by the readout electronics” explained Alastalo, “In fact, the WORM is just a resistance to be measured, and its bit size can be very small. It could be read using energy converted from RFID or an NFC reader” he added. An interesting feature of this resistive WORM memory is that it could be read in a contactless fashion too. Instead of physically contacting the bits to measure their resistance, the bit resistance could be read through a capacitive near-field measurement with a sweep-over reader device. As it is further testing and demonstrating the memory for different applications, VTT lab is searching for a partner to commercialise its patented process. A clean MIPS slate for academia By Julien Happich By letting universities study its MIPS RTL code and explore a real working MIPS CPU, Imagination Technologies seeks academia’s attention and hopes to nurture a new wave of MIPS-literate graduates into their future engineering roles. The company is not only opening up its RTL code for all to scrutinize, it has come up with a full teaching package with an FPGA-ready deliverables under the name MIPSfpga. EETimes Europe caught up with Robert Owen, Imagination Technologies’ Worldwide University Programme (IUP) Manager to understand how the company came around this bold decision regarding IP disclosure. “The MIPS architecture was originally developed at Stanford University in the early 1980s. It has been the teaching architecture of choice for decades because of its elegant true RISC design, epitomized by Dr. David A. Patterson and Dr. John L. Hennessy in their book, ‘Computer Organization and Design’”, likes to remind us Owen. “Many computer science and computer engineering courses teach CPU architecture based on MIPS which has been much publicized and well documented since its first inception in academia”, noted Owen, “so it is not as closely guarded a secret as other processors, and in most cases, researchers know what is inside”. Owen admits it was not an easy decision to take, and that letting free and open access to a fully-validated, current generation MIPS CPU, with non-obfuscated RTL code, yields some risks of fraudulent use. “Users that sign up our program have to accept a license whereby they are not allowed to turn the code into silicon for commercialization. Because they can get into the core, if they modified it and wanted to use a customized version, they would have to consult us”, clarified Owen. “It is possible that this would trigger some illegal copies, but we’ll monitor foundries closely” he added. Owen sees this new program as a way to reenergize the use of MIPS in education. “MIPS has been around in academia for a long time, but its use has been fading slowly”, explains Owen. “Academics are often disconnected from the commercial world, and most of them are not even aware that MIPS was acquired by Imagination Technologies who is now investing a lot to develop the architecture further with lots of new clever ideas, so it is important that we make a statement, carry-on using MIPS, it has a bright future”. 18 Electronic Engineering Times Europe May 2015 www.electronics-eetimes.com


EETE MAY 2015
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