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Verifying the RF antenna design Once you have achieved a true phasecoherent system, you can now focus on the critical tests needed to verify the RF antenna design. When testing multi-antenna transmitter systems, the MIMO recovery involves the separation of the multiple signal components in the presence of noise and interference. Table 1 shows the key measurements to validate the RF antenna design. It’s useful to start by viewing the RF signal from each antenna element to look for any fundamental RF power or timing impairments. Next, view the demodulation results Fig. 5: Example 4x4 modular system with phase-coherent signal generation and signal analysis for verification of multiantenna designs. including the IQ constellations, EVM result metrics, detected resource allocations, UE-specific RS weights, cell-specific RS weights and impairments as well as UE-specific and common broadcast antenna beam patterns. A multi-channel VSA system with precise time and phase synchronization allows for analysis of the multiple antenna elements including cross-channel performance and cumulative EVM. The main objective of receiver testing is to make performance measurements on the entire receiver. There are many factors that can influence the receiver’s performance and this can be especially challenging when multiple receivers are used in MIMO tests. Often simulation of the MIMO transmitter system is needed. A multi-channel VSG system can simulate complex MIMO and beamforming waveforms with cross-carrier scheduling in up to 8x8 MIMO. If inter-band carrier aggregation is combined with 8x8 MIMO, it’s possible to have up to 16 synchronized signal generators. Once you have established a multi-channel synchronized signal simulation environment, then the standard measurements can be performed on each receiver chain separately and the MIMO performance can be verified. Validate RF antenna designs • RF performance for up to 8 antenna elements including measurements like occupied bandwidth, spectral emissions mask, power, spurs, adjacent channel power • Crosstalk/Isolation, Time Alignment Error (TAE) • Demodulation measurements to verify the IQ constellations and modulation quality with EVM • Baseband encoded beamforming weighting algorithm correctness • Beam patterns w/ cell-specific RS power, EVM, timing, phase, symbol clock, frequency error • Beamforming gain Summary As wireless standards continue to evolve, enhanced multiantenna designs that include MIMO and beamforming will become even more common, placing greater demands on the design verification. New 5G standards will include even tougher requirements such as millimeter-wave frequencies up to 80 GHz, wider transmission bandwidths up to 3 GHz, denser modulation schemes and more antennas to implement techniques like massive MIMO. These will place more demands on test system designs requiring wideband, multi-channel, phase-coherent test techniques. While configuring multi-channel phase-coherent measurement systems has traditionally been very difficult, today’s modular instruments with phase-coherent capability provide the needed synchronization, density, scalability for the future and tools for engineers to gain deeper insight to their designs faster. JTAG/Boundary-scan: The development of standards By PPeter van den Eijnden rompted by a change in device packaging almost 30 years ago (from through hole to surface mount) a group of like-minded test engineers met to consider the impact that these parts would have on testing their forthcoming assemblies – they called themselves JTAG or Joint Test Action Group and were formed from representatives of Philips, BT, TI, IBM, DEC and others. In most cases PCB testing at that time (mid 1980s) had been accomplished using ICT (In-Circuit Testers) for individual component and PCB testing, or functional testers that could mimic the environment of the UUT (Unit Under Test) to send/receive stimulus and response signals. The work of the JTAG committee however would change the test landscape dramatically. The fruits of their labour was the now familiar ‘Test Access Port and Boundary-scan Architecture’ (aka IEEE 1149.1), and it describes how an embedded serial scan register can access digital signal pins of its host device to either capture an input signal or propagate an output signal through the pin of the device while isolating its regular function. By applying test patterns across interconnections between devices, assemblies could be tested for open circuits and shorts. Soon after tests were being developed that could stimulate and check the interconnects to RAMs, Flash and other logic parts. A few years after that the JTAG TAP was being used access for configuring/programming PLDs FPGAs and microcontrollers. Peter van den Eijnden is Managing Director of JTAG Technologies - www.jtag.com www.electronics-eetimes.com Electronic Engineering Times Europe May 2015 27


EETE MAY 2015
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