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EETE NOVEMBER 2012

NEWS & TECHNOLOGY INTERCONNECTING CHIPS Inter-chip photonic wire bonding links support several terabits per second By Nick Flaherty A teAm oF reseArchers in Germany has developed a novel for high resolution. optical connection to replace wire bonds on a semiconduc- A femtosecond tor chip. the ‘photonic wire bonding’ developed at the Karl- laser writes the free- sruhe Institute of technology uses an etched polymer to make form waveguide connections in the range of several terabits per second and structure directly is suited perfectly for production on the industrial scale. the into a polymer technology could be used in high-performance emitter-receiver that is located on systems for optical data transmission and so reduce the energy the surface of the consumption of the internet. chip and the KIt Development of high-performance optical emitters and researchers used receivers integrated on chips has already reached a high level. a laser lithography But there have not yet been any satisfactory ways of bridging system made by the Nanoscribe company, a spinoff of KIT. the chips optically. “The biggest difficulty consists in aligning Prototypes of the photonic wire bonds reached very small the chips precisely such that the waveguides meet,“said chris- losses and a very high transmission bandwidth in the range of tian Koos, professor at KIt’s Institute of Photonics and Quan- infrared telecommunication wavelengths around 1.55µm and tum electronics (IPQ) and of microstructure technology (Imt). in the first experiments, the researchers saw data transmission the team tackled the problem from the other side: the re- rates of 5tbit/s. Potential applications of photonic wire bonds searchers first fix the chips and then structure a polymer-based lie in complex emitter-receiver systems for optical telecommu- optical waveguide to fit. To adapt the interconnection to the nication as well as in sensor and measurement technology. KIt position and orientation of the chip, the scientists developed researchers now plan to transfer this technology to industrial a method for the three-dimensional structuring of an optical application in cooperation with partner companies. waveguide using a technique called two-photon polymerization Bandwidth is key as Altera plans for the end of copper backplanes By Nick Flaherty BANDwIDth Is the Key DrIver for Altera’s next generation of tions on the die.” this embedded instrumen- FPGAs as copper gives way to optical backplanes, says its head tation is vital for getting the bandwidth of technology. Improving the I/o bandwidth to support 28Gbit/s performance and is a combination backplane links and a new digital signal processing architecture of hard and programmable el- that focuses on the bandwidth are both key elements of the ements, providing self-calibra- 20nm products that will be launched next year with production tion and an adaptive engine in 2014 said Brad howe, senior vice president of research and to automatically optimise the development at Altera. bandwidth. But the move to 56Gb/s backplane technology is important as the new DsP architecture is also backplanes will move from copper to optical as a result, he says. vital for making the most of the incom- “we think at 56G you won’t see copper backplanes anymore, it ing data. “the DsP blocks have been re-architected for a more will be optical,” he said. “this is the interim step to 56G which is efficient implementation as well as the gains you would expect an architecture we have already put together.” he sees it taking from 20nm,” said howe. “I think in many ways our DsP archi- two to three years for the 56G standard to be settled, which sits tecture plateaued in prior generations and we haven’t pushed well with the mainstream production of the 20nm technology. “It the boundaries because of the bandwidth, and we are now able tends to play well with FPGA technology when the standard is in to provide that.” The new architecture is providing five times the flux and we can help enable that industry,” he said. The density performance of the current 28nm devices with over 5tFLoP/s of and performance at 20nm now allows the capabilities to be on single precision floating point DSP processing. the die. “we are big believers in this being done monolithically as Despite a focus on monolithic devices, howe also sees 3D this provides signal integrity but we have done a fair bit of innova- stacking of chips as a key way forwards for more bandwidth. tion in on chip instrumentation with an embedded eye viewer so “eventually we will get to tsv die but that won’t be mainstream you can see the performance of the link and logic analyser func- for a while,” he said. 12 Electronic Engineering Times Europe November 2012 www.electronics-eetimes.com


EETE NOVEMBER 2012
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