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EETE NOVEMBER 2012

NEWS & TECHNOLOGY NEXT GENERATION NODES Globalfoundries’ 14-nm is ‘low-shrink’ node By Peter Clarke The 14XM FinFeT manufacturing process node being intro- use as much as possible of earlier designs. That strategy would duced by Globalfoundries for volume production in 2014 is aimed produce the unusual prospect of manufacturing transition that at reducing power consumption, but it will provide users with little would not be driven by die size reduction and cost saving. “The or no size reduction over the previous 20-nm planar bulk CMOS value proposition is power-performance and not die size,” Chian node. Such a transition between manufacturing process nodes said. he also told delegates at the conference: “A fast migration – without a die footprint shrink as a clear cost saving as a driver – is a major part of the offering.” will be a first in the history of IC miniaturization. But he pointed out that because current drive strength will be But Mojy Chian, senior vice president of design enablement, told increased in FinFeTs compared with 20-nm planar transistors the international electronics Forum in a presentation “the normal designers may have the option to resynthesize a design and use ecomomics are dead,” with the value proposition shifting strongly smaller cells from a design library for some aspects of a design. towards scaling the performance and operating voltage while He said that use of different-sized cells could allow for some size physical scaling moves towards being carried more by 2.5-D and reduction although whether it was possible for the circuit as a 3-D packaging. whole and the amount would be circuit-specific. Globalfoundries’ next process has been labeled XM standing Chian expressed confidence that the14XM process would be for extreme mobility indicating the company expects to provide introduced without the cost and uncertainty of waiting for ex- market-leading performance and power consumption. The power treme ultraviolet (eUV) lithography. “The back end is the same as consumption benefit is benchmarked at a 40 to 60 percent 20LPM. This can all be done with double-patterning,” said Chian. reduction in active power consumption, Chian told at the confer- intel pioneered the commercial manufacture of FinFeTs with ence organized by consultancy Future horizons Ltd. a 22-nm process that has been in production for nearly a year. Globalfoundries is being aggressive on the introduction of However, that process has been criticized for only offering a the 14XM node – its first deployment of fin-shaped transistors single transistor threshold voltage, placing constraints on design- – expecting to bring it in just one year after its 20-nm CMOS. ers and not achieving looked for reductions in power consump- however, to do that the company is keeping the middle- and tion. intel Corp. has announced second interation 22-nm FinFeT back-end metallization the same as that used in the company’s manufacturing process for volume manufacture of system-chips 20LPM process and substituting FinFeTs for planar transistors. in 2013. Chian indicated that 14XM would be designer friendly. To ease rapid time to market Globalfoundries is enabling the use “We do plan to offer multiple threshold voltages. We do not ex- of ported iP blocks which will often have the same area footprint pect any design constraints. however Vt is quantized so design- in 14XM as in 20LPM. Chian said this will allow developers to ers have to recognize that.” 20nm and CoWoS reference flows enable next generation chip designs By Julien happich TSMC hAS DeLiVereD two foundry-first reference flows sup- The CoWoSTM reference Flow enables 3D iC multi-die porting 20nm and CoWoS (Chip on Wafer on Substrate) tech- integration, allowing a smooth transition to 3D iC with minimal nologies, within the Open innovation Platform (OiP). changes in existing methodologies. it includes the management TSMC’s 20nm reference Flow enables double patterning of placement and routing of bumps, pads, interconnections, technology (DPT) design using proven design flows. Lead- and C4 bumps; innovative combo-bump structure; accurate ing EDA vendors’ tools are qualified to work with TSMC 20nm extraction and signal integrity analysis of high-speed intercon- process technology by incorporating DPT aware place and nects between dies; thermal analysis from chip to package to route, timing, physical verification and design for manufactur- system; and an integrated 3D testing methodology for die-level ing (DFM). The new silicon-validated CoWoS reference Flow and stacking-level tests. enables multi-die integration to support high bandwidth and low The Custom Design reference Flow enables DPT in 20nm power in 3D IC designs. The CoWoS flow also benefits design- custom layouts. it provides solutions to 20nm process require- ers by allowing them to use existing, mainstream tools from ments, including a direct link with simulators for the verification leading eDA vendors, claims TSMC. of voltage-dependent DrC rules, and integrated LDe solutions Tools with DPT aware capabilities reduce design complex- and handling of hKMG technology. rF reference Design Kit ity and deliver the required accuracy. DPT enablement includes provides new high frequency design guidelines. These consist pre-coloring capability, new rC extraction methodology, DPT of 60GHz RF model support, high performance Electromagnetic sign-off, physical verification and DFM. In addition, TSMC and (eM) characterization that enables customer design capability its ecosystem partners design 20nm iP for DPT compliance to through the examples of 60GHz front-to-back implementation accelerate 20nm process adoption. flow and Integrated Passive Device (IPD) support. 8 Electronic Engineering Times Europe November 2012 www.electronics-eetimes.com


EETE NOVEMBER 2012
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