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EETE NOV 2013

IMEC TECHNOLOGY FORUM Imec opens its toolbox: finer pitches, faster lanes, power and fancy stuff By Julien Happich an awful lot of exciting new projects can crop up at large-scale research facilities such as those hosted on the imec campus. During a two-day technology update held at its headquarters in Leuven, Belgium, the company opened its toolbox and showcased possible business opportunities enabled by new process capabilities combined with open thinking. 3D versus 2.5D IC integration Of course, 3D IC integration was on the menu, with program director for 3D system integration Eric Beyne presenting imec’s latest packaging experiments and warning us about hidden yield costs. Imec has proven the suitability of tin-tipped 20μm pitch copper μBump interconnects and backside revealed copper TSVs to be used as μBumps for multiple die stacking up to six layers. But thermal management remains a limitation for stacking dies as power density increases too, warned Beyne, BEOL copper/ oxide damascene silicon interposer technology with 2x2μm copper tracks supports 200Mbit/s. not just for processors but also for DRAM whose data retention decreases with temperature. So an alternative stacking option is to link multiple dies on an interposer, with fine pitch interconnects. The so-called 2.5D interposer technology is very cost sensitive as it adds another Tin-tipped 20μm pitch copper μBump interconnects. stacked ICs. layer and processing step, what’s more, the longer planar interconnects increase resistive losses and delays, adding capacitance too. Based on Wide-I/O memory-logic interconnects requirements respecting the Jedec Standard JESD229 (1200 μBumps per chip, four 128-bit channels consisting of 6 rows with 40 μm pitch by 50 columns of 50 μm pitch), imec simulated various approaches on a 10x20mm interposer. An advanced high density laminate build-up with line sections of 10x10μm linked by 15μm diameter vias took 8 routing layers with an average wire length taking more than 80% of the die spacing. A semi-additive copper and photo-patterned dielectric redistribution layer build-up with line sections of 5x5μm and vias 7μm in diameter, took half the number of routing layers with an average wire length over 66% of the die spacing. The finer silicon interposer option, using a back-end-of-line (BEOL) copper/oxide damascene technology with line sections of 1x1μm and 1μm vias only required two routing layers and the average wiring length was equal to the dies’ spacing on the interposer. Imec has validated its BEOL copper/ oxide damascene silicon interposer technology at 200Mbit/s by connecting real chips with 2x2μm copper tracks, with excellent eye diagrams. The trade-off between vertical 3D stacking and side-by-side die stacking on an interposer has to be carefully evaluated, explained Beyne, not just for performance, but also for the costs associated with different testing, assembly and logistics scenarios and the overall yield results. The test flow of each stacking option must be optimized based on yield and cost parameters of the individual components being assembled. This evaluation and the optimization of the 3D stacked IC test flow is not trivial, costs can soar if the yield drops due to inadequate testing steps. For this purpose the Delft University of Technology (TU Delft) and imec have co-developed 3D-COSTAR, a test flow cost modelling tool for 2.5/3D Backside revealed copper TSVs stack up to six layers of dies. 12 Electronic Engineering Times Europe November 2013 www.electronics-eetimes.com


EETE NOV 2013
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