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EETE NOV 2013

AUTOMOTIVE ELECTrONICS Automotive drives new processor architectures By Nick Flaherty arm’s latest procesor architecture owes a lot to its automotive customers. It may seem strange at first, but while the V8-R architecture targets real time and security applications, it is particularly aimed at the automotive market. Virtualization is the key theme, both for the ARM v8-R but also for Imagination Technologies’ new Warrior cores. At the same time XMOS Semiconductor is also seeing automotive designs driving demand for Ethernet AVB on its Xcore multicore controller. ARM v8-R will be used for the next generation of ARM R cores that are currently used for ASIC designs with automotive and large industrial customers. Unlike the 64-bit V8-A architecture for applications processors such as the Cortex-A53 and A57 it will be 32-bits, but it adds the same ability to run Linux and Android ‘out of the box’ alongside security and virtualization enhancements. Both of these tackle the issue of the memory management unit (MMU) which Imagination has also had to address. “Over the last two years we have been planning how to apply the new technology to embedded applications,” said Richard York, director of embedded processors at ARM. “Talking to people in the automotive and industrial markets, they have big software problems that microcontrollers don’t help them solve, such as different levels of safety, combining rich operating systems with real time operating systems, legacy software and software form lots of different sources.” A key point is that the MMU will be 100% architecturally identical to the A8 version to run the wide range of software being developed for mobile applications, and this has been demanded by the automotive customers looking to build infotainment systems that also connect to the car’s networking infrastructure. Underneath that, virtualization hardware will allow hypervisors to run unmodified on the core with only one level of translation to support both mainstream operating systems such as Android alongside and RTOS. At the same time XMOS Semiconductor expects to receive automotive qualification for its multicore controller by the end of the year. The xCore 32-bit architecture provides a deterministic, software programmable I/O capability that has been adopted in robotics and increasingly in automotive as Ethernet AVB starts to gain traction. XMOS is also adding an ARM Cortex-M3 alongside its cores to tap into the ecosystem of ARM software, and the key is that designers can easily add high performance I/O such as multiple Ethernet AVB interfaces alongside the ARM as the controller. For the xCore eXtended Architecture (XCore-XA) XMOS is combining seven of its deterministic xCore processors with M3-based silicon from Energy Micro which was acquired earlier this year by Silicon Labs, using two dies in a single package. The Energy Micro devices have multiple low power modes and XMOS has enabled the M3 core to operate as a core and use those low power modes. This gives a range of processing from 100nA in deep sleep mode to 150mW with all cores operating and handling 500MIPs. The deal allows XMOS to tap the existing eco-system of ARM binary software and allows developers to add softwaredefined peripherals using the XCore tools and IP, says Nigel Toon, CEO of XMOS. “The xCORE-XA extended architecture redefines what embedded developers can achieve using a programmable platform,” he said. “Adding the Cortex-M3 technology from Silicon Labs as part of the xCORE-XA products allows customers to include ARM binary code and to create unique end products with the lowest energy consumption. We believe xCORE-XA represents a completely new class of programmable SoC. Now we can bring system level programmable configuration with hardware levels of real-time performance to low-energy battery-powered applications, configured and programmed completely in software.” Designers can also add real-time data-plane plus control processing and DSP blocks, using multiple xCORE processor cores, with the ARM available to run larger control plane processing software such as communication protocol stacks, standard graphics libraries, or complex monitoring systems. “ARM believes that xCORE-XA represents a significant step forward for embedded systems, allowing engineers to create an integrated SoC that is configured completely in high level software,” said Nandan Nayampally, vice president of Application Systems Marketing at ARM. Imagination Technology has also launched its latest core, using the Release 5 of the MIPS architecture to tackle the same challenges as ARM v8-R in re-using high level operating systems such as Android while adding virtualization and security. This is the first implementation of release 5 and comes as Imagination completes the takeover of MIPS. The new MIPS cores come in three varieties within the ‘Warrior’ family, all using Release 5. The P class takes the proAptiv cores on, while the I and M class map to the InterAptive and MicroAptiv cores. The first core is the 32-bit P5600 which extends the address pace to 40-bits for more complex software and adds the full 128 SIMD (single instruction, multiple data) design for digital signal processing, imaging and media that was part of Release 5. “We fully understand we are not the first in offering 128-bit SIMD but sometimes there are benefits in not being first,” said Mark Throndson, director of processor marketing at Imagination Technologies. “In this case we take a very RISC-like view of SIMD and designed it to be supported and programmed in high level languages. For the complete set of compiler vector operations we have 100% native instruction mapping in the GMU 22 Electronic Engineering Times Europe November 2013 www.electronics-eetimes.com


EETE NOV 2013
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