Page 44

EETE NOV 2013

ANALOG design Mitigating antenna effect in integrated circuit design By Gagan Kansal and Ajay Sharma The density and speed of ICs have increased exponentially for several decades, following a trend described by Moore’s Law. While it is accepted that this exponential improvement trend will end, it is still not clear that exactly how dense and fast integrated circuits will get by the time this point is reached. With the increasing density and Gate oxide width reducing with each technology node, many effects which were common in VLSI are becoming important and difficult to manage. One of those effects is Antenna Effect. The semiconductor technology has been continuously improved over the past two decades and has led to ever smaller dimensions, higher packaging density, faster circuits, and lower power dissipation. Antenna effect The Antenna Effect or Plasma Induced Gate Oxide Damage is an effect that can potentially cause yield and reliability problems during the manufacturing of MOS integrated circuits. Presently Lithographic processes for IC fabrication use ‘Plasma etching’ (or ‘dry etching’). Plasma is an ionized/reactive gas used to etch. It allows super control of pattern (shaper edges / less undercut) and also allows several chemical reactions that are not possible in traditional (wet) etch. But life is not always so good. Several unwanted effects also accumulate. One of them is the charging damage. Plasma charging damage refers to the unintended high-field stressing of the gate-oxide in MOSFET during plasma processing. During Plasma Etching high amount of charge can collect on poly and metal surfaces. Through capacitive coupling, large electric fields may develop over gate oxides, resulting in stresses that cause oxide breakdown and shifts in threshold voltage Vt of the device. The collected net charges are channeled to the gate as shown in figure 1 where it is neutralized by the current tunneling across the gate-oxide. Clearly, the size of the conductor exposed to the plasma plays a role in determining the magnitude of the net charge collection rate and therefore the tunneling current. This is the so called “antenna effect”. The area ratio of the conductor to the oxide under the gate is the antenna ratio. The antenna ratio, in a rough sense, is a current multiplier that amplifies the tunneling current density across the gate-oxide. For a given antenna ratio, a larger tunneling current is supported when the plasma density is higher. Higher tunneling current means higher damage. For the conductor layer pattern etching processes, the amount of accumulated charge is proportional to perimeter length. For ashing processes, the amount of accumulated charge is proportional to area. For contact etching processes, the amount of accumulated charge is proportional to area of via. Classically, the antenna ratio (AR) is defined as the ratio of total area and/or perimeter of conducting layer attached to gate, to the total gate area. The classical theory predicts that the amount of degradation is directly proportional to the AR, with the charging effect identical for each metal layer. However, AR was found to have little or no dependence on antenna effect. There are also layout dependencies that need to Figure 1 be considered. Layout dependency of charging damage The extent of charging damage is a function of the geometry that is connected to the gate-dense-line antennae. But it is also affected by electron shading effects, by etch rate differences in reactive ion etching (RIE), by plasma ashing and oxide deposition (plasma-induced damage or PID). Hence a new model of antenna effect should be considered taking into account the etch time factor as shown in formula 1. A better predictor of antenna effect can be expressed with formula 2. According to this new model, the PID has little to no dependence on AR, but the ratio of antenna capacitance to gate capacitance is good indicator of PID. The plasma-induced damage depends upon the frequency of the plasma power source. For oxides under 4nm, plasma-induced damage is not particularly sensitive to stress current. Increasing the dielectric constant of the gate without increasing J can decrease the PID. Gagan Kansal is Layout Design Engineer at Freescale Semiconductors, Noida, India. - www.freescale.com Ajay Sharma is Lead Engineer at Freescale Semiconductors, Noida, India. Formula 1 Formula 2 36 Electronic Engineering Times Europe November 2013 www.electronics-eetimes.com


EETE NOV 2013
To see the actual publication please follow the link above