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EETE NOV 2015

nanotube transistors Switch to carbon at 3-to-5 nanometer By R. Colin Johnson If a breakthrough in carbon nanotube transistors from IBM Research pans out, the hard stop of 2028 in International Technology Roadmap for Semiconductors (ITRS) is about to get extended. IBM says it has found a way to scale down the channel length to the 1.8 nanometer node (four technology generations away) and beyond to the angstrom level eventually. If they are right, Moore’s Law may now be extended to the sub-nanometer angstrom (1/10th of a nanometer) levels using the same extreme-ultraviolet (EUV) complementary metal oxide semiconductor (CMOS) process technologies already in place. “The 1.2 nanometer wide carbon nanotube channel is already proven,” Shu-Jen Han, IBM manager of nanoscale science and technology at its T.J. Watson Research Center (Yorktown, Heights) told EE Times in an exclusive interview. “The major issue for scaling, not only for carbon nanotubes, but for silicon and III-V materials indium, gallium, arsenide is the contact— which is no longer scaling.” “With our recent breakthrough,” said Han, “we now know how to scale the contact so it is no longer the limiting factor for carbon nanotube transistors. Our new contacts are measured in angstroms and have just just 36 k-ohms of resistance, including both ends.” The breakthrough technique was a long time coming, but according to analyst Richard Doherty, research director at Envisioneering (Seaford, N.Y.), that was only to be expected. “After all, if you remember that it took about a decade to go from point-contact transistors at Bell Labs to planar transistors at Fairchild and Intel, it’s not surprising at all that it took IBM a decade too,” Doherty said. IBM’s proof-of-concept chip has nine-nanometer channels, but before the breakthrough the contacts were giant in comparison. Now IBM has found a way to make smaller contacts enabling them to scale down the channel length to the 1.8 nanometer node (four technology generations away) and beyond to the angstrom level eventually. Each nanotube carries only about 15 microamps, but IBM plans to solve that problem by just using as many nanotube channels in parallel as required Schematic showing the fabricated nanotube transistor with an end-bonded contact and a contact length below 10 nm. (Source: IBM Research, used with permission)X for the type of drive a transistor needs for a particular location in a design. “We can place nanotubes in parallel with about a 8-to-10 nanometer pitch using self-aligning techniques,” Han revealed to EE Times. “We deposit them using a PVD physical vapor deposition process, then use high-temperature annealing - a metallurgical process akin to microscopic welding -to secure the channel contacts at each end.” Analyst Doherty was impressed by IBM’s “welding” tech- The reflection of Roland Germann, manager, Nanotechnology Center Operations at IBM Research - Zurich in the clean room. (Source: IBM, used with permission) Cross-sectional transmission electron microscope (TEM) image showing the fabricated nanotube transistor with an end-bonded contact. (Source: IBM Research, used with permission) 14 Electronic Engineering Times Europe November 2015 www.electronics-eetimes.com


EETE NOV 2015
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