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Industrial robotics FPGAs and functional safety in industrial applications By Joe Mallett The increasing adoption of automation on the factory floor is a key driver for more processing bandwidth, integration of industrial-specific communications, and functional safety. The integration of FPGA devices into applications found on the factory floor, like programmable logic controllers (PLCs), industrial networking switches, and motor controllers is increasing due to their long lifetimes, high processing bandwidth, and flexibility to integrate many IP technologies. Often these automation technologies enabled by FPGAs translate to greater interaction between people and machines, calling for additional functional safety. To facilitate building functionally safe designs, robust synthesis tools that support defined methods are needed. One such tool is Synplify Premier, which provides FPGA designers with technologies that enable functional safety capabilities into their products. The operation of FPGA-based products in harsh conditions ranging from high temperatures to high radiation environments can cause errors to be introduced. This creates a growing need to utilize special design techniques to detect in-system errors and to recover to correct operation. Synplify Premier provides Duplicate with compare example (Source: Synopsys). designers with the ability to build-in these safety features to help mitigate errors and, ultimately, achieve greater design reliability. The range of solutions enabled through Premier’s design for high reliability capabilities include safe and fault tolerant finite state machines (FSMs), redundancy-based mitigation, support for I/O replication, memory error correction circuitry, and error monitors to trigger error correction. These capabilities can be used in any combination to suit the design. By utilizing one of the redundancy-based mitigation strategies, a designer can create a circuit design that can be duplicated and compared. Premier will automatically duplicate the circuit and add the compare circuitry with an error flag output that can be tied to a local register accessible by the embedded software for system level control within the functional safety software stack. The embedded system software can read the error condition and respond with the correct recovery scheme. In addition to redundancy techniques, designers need to take care with FSMs, which can become stuck in an invalid, and potentially disastrous, state. A soft error can force the state machine into an illegal state, so the tools must be capable of taking the original state machine representation as defined and augmenting it with the ability to detect and mitigate induced errors. With today’s small silicon geometries and higher reliance on “safe” designs, induced soft errors impose an increasing threat to reliable operation in multiple applications - not just in industrial environments, but also in things like automotive applications. By utilizing redundancy, developing safe sequential logic, and creating fault-tolerant state machines with custom error mitigation logic, designers can protect their FPGA-based designs from soft errors. As more applications require implementing functionally safe features, even at sea level, tools like Synplify Premier become invaluable to designers. Joe Mallett is a senior product marketing manager for FPGAbased synthesis software tools at Synopsys – www.synopsys.com Searchable 4K mobile imaging soon a commodity By Julien Happich Cadence has just unveiled its latest image and video processing DSP core, the Tensilica Vision P5, boasting a 13X performance boost at a fifth the energy consumption compared to its previous offerings. The new DSP core was built from the ground up for applications requiring ultra-high memory and operation parallelism to support complex vision processing at high resolution and high frame rates. As such, it is well suited for off-loading vision and imaging functions from the main CPU to increase throughput and reduce power. End-user applications that can benefit from the DSP’s capabilities include image and video enhancement, stereo and 3D imaging, depth map processing, robotic vision, face detection and authentication, augmented reality, object tracking, object avoidance and advanced noise reduction. The Tensilica Vision P5 DSP core includes a significantly expanded and optimized Instruction Set Architecture (ISA) targeting mobile, automotive advanced driver assistance systems (or ADAS, which includes pedestrian detection, traffic sign recognition, lane tracking, adaptive cruise control, and accident avoidance) and Internet of Things (IoT) vision systems. The advances in the Tensilica Vision P5 DSP further improve the ease of software development and porting, with comprehensive support for integer, fixed-point and floating-point data types and an advanced toolchain with a proven, auto-vector- 40 Electronic Engineering Times Europe November 2015 www.electronics-eetimes.com


EETE NOV 2015
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