022_EETE-VF

EETE OCTOBER 2012

DESIGN & PRODUCTS DIGITal SIGNal PROCESSING Fig. 3: The B4860 SoC. This reduces the number of required complex multiplications. Each SC3900 DSP core has four DMUs each with eight 16x16 MAC per DMU and performs at 38.4 milliard multiply ac- Conclusions cumulates per second (GMACS) at 1.2 GHz yielding a maximum In this paper, we have demonstrated efficient implementa- total performance of 230.4 GMACS per device. tion of 4x4 complex matrix inversion on Freescale advanced The B4860 also contains a multi-accelerator platform engine SC3900 flexible vector core, which is a highly efficient DSP for a (MAPLE-B) that performs Turbo decoding, Viterbi decoding, variety of mathematical calculations. This core typically has four Fast Fourier Transform, Discrete Fourier Transform, MIMO to eight times the cycle performance relative to the previous equalization, WCDMA/HSPA chip rate and path search and generation SC3850 core, performing thirty two 16x16 bit fixed- CRC. point multiply-accumulate operations per cycle. Complex matrix A block diagram of the B4860 is shown in figure 3 while fig- algebra calculations are performed efficiently utilizing its four ure 4 shows a block diagram of the SC3900 cluster. DMU, advanced ISA and the 38.4 GMAC per second. About the B4860 The QorIQ Qonverge B4860 system-on-chip is designed for next generation, multi-standard wireless base stations. Based on 28 nm pro- cess technology, the B4860 targets macro cell base station designs for broadband wire- less infrastructure. The B4860 combines four 64 bit, dual- threaded e6500 cores built on Power Architecture technol- ogy, six StarCore SC3900 16bit 32MAC/cycle cores and MAPLE-B baseband accelera- tion processing engines. It is designed to adapt to the rapidly changing and expanding standards of LTE (FDD and TDD), LTE- Advanced and WCDMA and supports different standards Fig. 4: SC3900 Cores Cluster. simultaneously. 22 Electronic Engineering Times Europe October 2012 www.electronics-eetimes.com


EETE OCTOBER 2012
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