Page 38

EETE OCTOBER 2012

DESIGN & PRODUCTS DIGITal SIGNal PROCESSING The application contains many vector additions and subtrac- tions on identical operands. Therefore an add-subtract butterfly instruction was added to the processor. Finally, separate data- move instructions were introduced between the vector register- file and the transposable register-file. With these architectural optimizations, the instruction cycle count reduced below the available budget. at this point, an rTL hardware implementation was generated and synthesized for the first time. This revealed a total area of 90K gates for the Jema asiP alone, whereas the total budget for both asiPs was only 100K gates. In a third iteration, the JEMA architecture was further optimized to reduce the gate count. This was achieved Table 1: Manpower spent on the dual-ASIP JPEG encoder by splitting the general-purpose register-file into two smaller design. files with fewer access ports. Also, the instruction word was encoded in a more application-specific way, reducing from 48 to tuning of the nmL model, rTL generation and logic synthesis. 28 bits. With these optimizations, Jema’s gate count reduced Admittedly, the design was made by an experienced engineer. to 65K gates, with no impact on the instruction cycle count. yet, this case study shows the importance of retargetable asiP a similar design process was applied to the JemB asiP. design tools in the development process of heterogeneous Here, the final outcome was a scalar architecture with signifi- multicore socs. Based on a formal processor description lan- cant instruction-level parallelism. The architecture was special- guage, these tools are not restricted to parameterized template ized by introducing three separate data-memories of different architectures, and thus enable rapid and true architectural word-lengths, and an arithmetic and logic unit with dedicated exploration. For each architecture, a software development kit instructions for bit manipulation tasks. with an optimizing c compiler, and a low-power rTL hardware model are automatically generated. Morale of the story asiPs are a key technology in the design of heterogeneous The manpower spent on the dual-asiP JPeG encoder design multicore socs, because they reconcile what are often con- was as shown in table 1: sidered contradictory requirements: Performance, Power and Architectural exploration included C compilation, profiling, Programmability – theThree P’s of soc design. PacketVideo server software integrated into transcoding chip for home multimedia The STiH416 Orly real time transcoder SoC uses the Twonky server software from PacketVideo so that content from many different sources can be streamed to many different de- vices in the home, regardless of the original content format or the screen resolution of the display de- vice. The diversity of technologies currently used throughout the multimedia world presents many challenges to achieving the vision of sharing content from any source on any other consumer applica- tion. For example, today most mobile devices are still unable to play TV content and most TVs cannot play videos taken from mobile devices. orly provides multi-format transcoding and broadband with the ability to bridge the many different multimedia scenarios, each of which has their own standards and resolutions. The second advance is the integration of the media server that complies with the universally accepted dLna (digital Living network alliance)/uPnP (universal Plug and Play) standards that can discover and communicate with any devices in the home. This allows integrated broadcast and over-The-Top (oTT) internet content, 3d gaming and TV, social videoconferencing, and home automation by commu- nicating with other home devices and sensors. STMicroelectronics MPL AG, Täfernstr. 20, CH-5405 Dättwil/Switzerland ww.st.com Phone +41 56 483 34 34, Fax +41 56 493 30 20 28 Electronic Engineering Times Europe October 2012 www.electronics-eetimes.com


EETE OCTOBER 2012
To see the actual publication please follow the link above