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DESIGN & PRODUCTS aNalOG DESIGN and applying a slightly different set of parasitics and silicon area, and creates rules and constraints. The net result is devices optimized for high yield. The re- that the number of re-spins of analogue sulting design primitives are re-usable, and mixed-signal designs are increas- and based only on the manufacturing ing, creating pressure to standardize design rules for the specific technology and automate. node. Retargeting the components to The EDA industry offers varying a new technology node simply requires degrees of increased automation with the user to input the manufacturing some vendors attempting to inject more rules for that technology and regenerate parameterization at the device level. the devices and primitives. So it is pos- The problem with this approach is that sible to very quickly move a design to it does not address the layout, which a new technology node or to a different is the most time-consuming element of foundry. analogue design and the element with most impact on quality. Large amounts Because this class of tool stops of time are still required to generate short of total automation, the layout en- structures by hand and the quality of gineer maintains complete freedom to the resulting layout varies depending fine tune the primitives themselves, and upon the skill of the individual engineer. to manually place and route them. HiPer DevGen is provided with basic default Some EDA providers have attempted values that meet the requirements of to automate the layout process almost 90% of analogue designs. For example, entirely. But this requires a high-level in a differential pair it will, by default, approach that may not take full account attempt to optimize the drain parasitics of the characteristics of the key building over the source parasitics. However, blocks, or lay them out with the correct in a circuit such as a down mixer, the considerations. In addition, the use source capacitance is more critical: the of global matching rules to the entire designer or layout engineer can easily layout can have a negative impact. change the relevant parameters, regen- For example, skilled manual designers erate, simulate the design and converge understand that a current mirror should on an optimal design approach. not be laid out in the same way as a Layout engineers maintain complete differential pair. freedom to manually place and route these structures in addition to be- None of these approaches can rival ing able to tune the output to specific the quality of results that can be at- requirements. Surpassing traditional tained manually. Most also suffer from a automation methodologies, this new fundamental problem, which is they re- layout approach dramatically improves quire the designer to enter a great deal layout productivity and reduces design of information upfront, such as circuit- cycle times while generating structures design constraints. As these constraints at a level of quality that consistently vary substantially from design to matches that of the most experienced design, this upfront investment of time layout engineers. produces little or no payback. Another advantage of this level of au- tomation is that the generation engine A more effective approach can be made ‘silicon-aware’, supporting Arguably a significantly more effective design for manufacture (DFM) rules and approach is to accelerate the layout producing yield-optimized devices with process by increasing the level of special design features such as double abstraction and automation, but with- contacts and vias. It can account for out losing the refinement that can be a number of increasingly important achieved by a designer. A tool such as artefacts that are produced by shrinking HiPer DevGen from Tanner EDA gener- device geometries. These include well ates ‘macro level’ cells: re-usable de- proximity effect, a phenomenon that sign primitives such as differential pairs, causes doping density to vary across current mirrors and resistor dividers, the width of an isolation well: this in that are often the most time–consuming turn means that a transistor’s electrical aspect of layout and are frequently also characteristics may vary according to the parts that are critical to the function- where it is placed within the well, and in ality of the silicon. particular if it is placed close to the well The tool applies matching techniques edge. to address common processing arte- Using an automated tool can also facts, produces the optimal solution for help designers to account for mechani- 44 Electronic Engineering Times Europe October 2012 www.electronics-eetimes.com


EETE OCTOBER 2012
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