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Displays & Interfaces C M Y CM MY CY CMY Fig. 1: Near noiseless circuit for interfacing a CCD to a high performance ADC but consumes 260mW, requiring that the surrounding network K dissipate about 40mW just to produce a level shift. Furthermore, it dissipates signal power in the relatively low value resistors required for low noise and for maintaining phase margin. These differential amplifiers as a result have low input impedance. Near noiseless ADC drivers for imaging By Derek Redmayne CCDs (charge coupled devices) and other sensors place heavy demands on digitizers, both in terms of sample rates, and in signal-tonoise ratio. The sensor output is typically a ground-referenced series of analog levels (pixels), possibly with transients occurring between the pixel boundaries. As the number of pixels increases, so does the sample rate of the ADC required to capture the image, with 20Msps pipelined ADCs sufficient for most high dynamic range applications. To ensure the highest SNR performance of the sampled signal, the drive circuitry for the ADC must provide low impedance, fast settling without introducing wideband noise and yet present high input impedance to the sensor. This article presents an interface circuit between the sensor and a high performance ADC that does not compromise the SNR performance. The LTC2270 16-bit pipelined ADC family is intended for high end imaging applications. The 84.1dB SNR of this family makes it attractive for imaging, but it also features very good SFDR—over 100dB. The input range is 2.1VP–P, significantly less than the output of most imaging devices, so attenuation and level-shifting is required. The inputs of these ADCs must be driven with a well-balanced differential drive. The single ended drive normally available from the sensor would force the internal virtual grounds to absorb common mode input current, which would cause degraded performance. These ADCs are also very low powered devices at 80mW/channel. Differential drive is actually fundamental to the low power operation since single ended drive would require additional power to maintain a stable internal reference point in the ADC. The devices’ 1.8V operation imposes an input range of this order, if nothing else, simply to stay away from the rails. It is important to stay away from the rails to prevent differential phase error that would be associated with the voltage variable capacitance of internal protection diodes. Selecting the differential amplifier Therein lies a dilemma: A differential amplifier capable of performing single ended to differential translation without compromising the SNR of the ADC will necessarily have low input impedance (or low value resistors) and as it must settle quickly to 16-bit accuracy, will likely consume something on the order of four times the power of the ADC itself. The LTC6409 differential amplifier is an example that produces good results, The buffer that would be required to present a high impedance to the CCD also presents a dilemma. It must be low noise, be capable of settling in less than 25ns, and be capable of slewing with enough dV/dt to maintain closed loop operation during transients. Additionally, it must be capable of driving the low input impedance of the differential amplifier. Yet, the application demands low power. This dilemma is even greater if there is the expectation that the amplifier operate from the single supply rail. Most differential amplifiers present a number of problems as they either need band-limiting after the amplifier to the extent that settling is compromised, or they are not very stable with a gain of less than one (a noise gain of less than two) and as such tend to ring. Many are not common mode compatible with the 1.8V ADCs or they do not have enough headroom to accommodate a double terminated filter, or a level shift after the amplifier. The LTC6404 is a good case to study. It is stable at unity gain, does not ring as do some, and could potentially be used with an attenuator after the amplifier, but the input referred noise is 1.5nV. This compares to 1.1nV for the LTC6409. The LTC6404 noise density peaks considerably above 100MHz, it consumes 175mW, and it is not really compatible with the 900mV common mode required by the LTC2270. If it were followed by a filter and level shift, the impedance would be such that you will dissipate some 80mW dropping voltage in the dividers. Derek Redmayne is Staff Scientist for mixed signal products at Linear Technology – www.linear.com 18 Electronic Engineering Times Europe October 2013 www.electronics-eetimes.com


EETE OCT 2013
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