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Displays & Interfaces Fig. 2: Prototype imaging board You could potentially operate the amplifier off +3.3V and –2V to resolve common mode compatibility and produce a larger signal swing without requiring a level shift after the amplifier. But the negative supply is not often palatable to designers. The settling time available to the amplifier may not be an entire clock cycle. The source may dictate this, but there is a disturbance produced by the ADC on the opposite edge of the clock and this would give the filter only ½-clock cycle to settle even if the amplifier were not otherwise disturbed. If the amplifier is disturbed by this event, it does not leave as much time for the filter to settle. A simple RC would require about 14 time constants to settle to 16 bits, and for 20Msps, this would result in a bandwidth of about 90MHz. As it happens, the amplifier will be disturbed to some extent by sampling and this means that the bandwidth of a simple post filter must be extended to 130MHz to 150MHz to allow for some settling of the amplifier in response to the disturbance. Unfortunately, this will pass noise in the region where the amplifier is peaking. A higher order filter may result in a more pronounced reduction of noise contribution from the earlier Nyquist zones, but will not necessarily settle very quickly. The scheme described herein can drive the 25Msps LTC2270 family with 84.1dB SNR and 17pF sample capacitors. Impedances can be raised and power consumption can be reduced at sample rates of 20Msps, and less. For sample rates higher than 30Msps, a more conventional topology involving a fast buffer, followed by a differential amplifier like the LTC6409 is required. The LTC6404-1 can alternatively be used in that case. The near noiseless suggestion The circuit in figure 1 shows a suggested drive scheme that results in almost no loss of SNR with the LTC2270 family, yet can settle to 16 bits within 1 pixel at 25Msps. The noise at –84.0dB (all included) is such that it will not necessarily be within 1 count in a single frame, but averaging multiple frames could resolve to 16 bits. The buffer amplifier (U2) is a current feedback amplifier used essentially as an emitter follower. The bulk of the output current is taken via R16, seemingly from the emitters, although power is delivered from the output. As the impedance looking into the inverting input is low compared to the feedback network, the output noise is attenuated at the inverting input and, as a result, the inverting input noise current does not contribute significantly. This amplifier has a voltage noise specification of 4.5nV/√Hz, although when used as a unity gain buffer, inverting input noise current in the minimum value feedback resistor produces 10.1nV/√Hz. However in this emitter-follower-like mode of operation, it appears to be on the order of 1.5nV/√Hz to 2nV/√Hz. There is a feedback loop around the amplifier and this amplifier imposes a minimum feedback resistor of 400Ω. However, at low frequency, the feedback impedance is 400Ω in parallel with R23 to reduce the excursion required at the output. But at high frequency, the feedback is the required minimum 400Ω. There is a minor amount of output power taken from the output, via R24, just to reduce the required excursion produced at the output. But this may not be required in many cases, for example where the video signal is 0V–4V, or less. There is provision for R24 just in case, in the future, U2 may be a different amplifier where it is practical to take power from the output. There are several possible alternatives depending on required slewing. A low noise fast settling FET amplifier could possibly be used on a single supply. With rail-to-rail amplifiers, it is likely that the positive rail must be 6V to avoid crossing through the transition region between two input stages, a region that causes distortion. If the LT1395 is used, 7.5V to 8V must be used for VCC and –2V for VSS, if intended to receive 0V–5V signals. A lower powered amplifier such as the LT6252 may be used if there is no need to settle through a full-scale step between pixels. Bad pixels however would bleed into following pixels. The presence of clock feed-through and the actual settling time available may limit these choices. The second amplifier is also an LT1395, but note that this cannot be a dual LTC1396, unless the application were to involve signals centered on ground potential. This second stage must operate on 5V and –5V in order to sink current and perform a level shift from ~2.5V common mode to 0.9V common mode, as well as provide differential drive by virtue of controlling the common mode. The noise and distortion contribution of this amplifier is largely rejected by the CMRR of the ADC as its influence is only common mode, assuming the network surrounding the amplifier is completely symmetrical - see the implementation board in figure 2. Fig. 3: Prototype 0.5 square inch 4-output power supply 20 Electronic Engineering Times Europe October 2013 www.electronics-eetimes.com


EETE OCT 2013
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