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EETE OCT 2013

Displays & Interfaces Fig. 4: Two tone test –7.022dBfs sinusoid at 70kHz, –7.01dB synchronous square wave at Nyquist We developed a power supply board that provides all four of the required voltages from a single 5V input - see figure 3. The power supply circuit is capable of powering four channels, yet produces no evidence of the 1.2MHz switching rate used by the LT3471—even at –125dBFS. As shown, this driver produces 84.0dB SNR combined with the ADC and including any contribution from the power supply board. The tests below were done with R1 at 75Ω, and a 50Ω source. This circuit should be suitable where CCDs either have an output impedance in the 50Ω–200Ω range, or where the charge transfer into a holding cap produces an effective impedance in the hundreds of ohms. The use of a fast FET buffer may allow very high source impedance. The capacitor C6, at 22pF, is required if the dV/dt during transients from the CCD exceeds the slew rate of the LTC1395 or if RFI is present. CCDs appear to tolerate capacitive loads of this magnitude. If the output stage of the LTC1395 is not capable of keeping up, conduction of input protection diodes would greatly reduce the input impedance. This conduction occurs in almost any feedback amplifier. And this would produce an error if a charge transfer mechanism were exposed to this input current, possibly even if buffered in the CCD. R21 is potentially desirable as source termination if the distance between C6 and the amplifier were extended. This topology is only practical with ADCs that have approximately 2VP–P input range and where the CCD signal is on the order of 0V–4V or 0V–5V. This takes advantage of the attenuation that is required to produce the balun action by controlling the common mode. This is analogous to the transmission line balun where high common mode impedance between input and output ports results in balanced drive if symmetrically terminated to AC ground. The filter as shown produces a Gaussian-like response, and is 3dB down at about 40MHz. The filter is replicated twice independently, in order to provide a symmetrical network that maintains the error contribution of U1 as common mode. R7, R4, and R17 and their counterparts satisfy the requirements for stability of U1, produce attenuation of the 0V–5V signal to ±1V, and produce a level shift. These elements can in fact be after the ADC and act as end termination, which allows somewhat faster settling. If there is a significant distance between the CCD and the ADC, simulation says that the transmission Fig. 5: Same applied power level at 70kHz, but removal of power at Nyquist path can be extended between a pair of 50Ω resistors replacing R16. If the distance is between 30cm and up to about 60cm, the cable should be 75Ω. The source termination resistor would then be 75Ω and the other side, 25Ω. PCB traces should be higher than 75Ω if possible. If this is intended to drive into the LTC2185, for example, a 350psec transmission path is possible. If the LTC2270 family is used, the 17pF sample capacitors require that this transmission line (T1 and T2 in figure 1) should be less than 40ps (about 1cm). Tests performed to satisfy that this will perform with CCD signals, besides digitizing small offset frequencies from ¼FS and ½FS at 20Msps and 25Msps, include: 300kHz –1dBFS sinusoid (–92dB SFDR 2nd and 3rd), representative of dV/dt in a CCD signal; as well as a near full scale square wave (10MHz and 5MHz) with a superimposed –20dB sinusoid at 200kHz, showing no distortion on the sinusoid resulting from the large synchronous excursion in pairs of “black and white pixels.” Note the appearance of two waveforms in the time domain plot in figure 4, caused by alternation between the two levels in the square wave every other sample. The inverse FFT window is zoomed in on the time axis, showing only the tone at Nyquist, this by selectively masking out the power in the 70kHz area. Figure 5 shows no apparent power change in the low frequency tone, still at –7.022dBFS and only relatively minor change in the distortion components. This proves the addition of a high amplitude square wave is not causing compression at the peaks. A 70kHz tone, superimposed on a ½FS square wave is believed to represent the dV/dt and settling scenario that would be representative of that seen in a CCD waveform sampled near the end of the pixel. If an ADC with high SNR is required in an imaging application, a single-ended to differential conversion is required to get the signal from the CCD to the ADC. The conversion must attenuate the signal swing and provide a very stable common mode output level without adding significant noise. The circuit presented here can do just that. Working with a low power ADC that has a data sheet SNR specification of 84.1dB, this circuit achieved 84.0dB—implying that the conversion was nearly noiseless. 22 Electronic Engineering Times Europe October 2013 www.electronics-eetimes.com


EETE OCT 2013
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