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as well as to implement the PHY and MAC functions within the protocol stack. While the beam forming itself is carried out using phase shifters in the RF stages, the processor needs to provide very rapid instructions to the phase shifters in order to control this in real time. The modem functionality is computationally intensive, as the protocol requires more than two Teraops/s of digital signal processing power. When prototype WiGig solutions were initially developed, the baseband was largely realised on fixed function hardware, but since then there has been a move towards software-defined architectures in order to provide additional application flexibility and extensibility. To implement two Teraops/s on a single processor would cause significant thermal problems (due to the need to clock such a processor at 10’s GHz), while on a conventional multicore system the chip real estate would be unmanageably large. WiGig also requires a complex digital sample rate of 2.64GHz, which is an order of magnitude higher than previous wireless standards, and this further complicates the optimum choice of processing architecture and, moreover, leads naturally to consideration of parallel processing architectures in order to support clock speeds compatible with today’s silicon technologies. Baseband architecture Blu Wireless has therefore developed a software-defined baseband that is specifically aimed at low-cost and powerefficient implementations of the WiGig standard. Although software-defined radio (SDR) platforms often provide for a wide spectrum of baseband standards to recoup the cost of the technology development, this approach is not appropriate for WiGig because of the substantial DSP processing required for the high sample rates. To balance the cost/efficiency trade-off, a domain of programmability approach was selected — this provides a constrained scope of useful WiGig programmability without losing Fig. 3: HYDRA WiGig modem architecture. applicability, and results in a near optimum solution for low cost products. The Blu Wireless HYDRA baseband technology – see figure 3 - utilises a heterogeneous multiprocessing architecture, mixing fixed function DSP blocks with highly optimised parallel vector DSPs. This mixture provides a pool of DSP processors and fixed function blocks that are arranged in clusters, which optimises data flow. Each cluster has a heterogeneous controller that automatically and optimally utilises these Modems     Modulation     FEC  code  rate     Data  rate     Sample  Rate     Single-­‐carrier     π/2-­‐  BPSK   π/2-­‐  QPSK   π/2-­‐  16QAM     OFDM     Spread  QPSK   QPSK   16  QAM   64  QAM     units, switching units off between executing tasks to preserve power. The high-level software uses a threaded data flow model, whereby software threads defining the wireless DSP pipeline are dispatched, in order, as a ‘virtual pipeline’ in a series of interlocking threaded sub-tasks. The controller automates the threaded data flow through the heterogeneous DSP resources. These subtasks are executed on each DSP unit, driven by data-flow completions that move data concurrently between them. Any arbitrary combination of dispatched virtual pipelines can be dispatched, and the real-time data flow defines the execution, timing and order. This approach is efficient both in utilisation and in power consumption, since dynamic power control of each individual unit ensures switch off in idling, and hence minimises power consumption. When realised on a 40nm CMOS process, this parallel vector DSP processor has a footprint in single-digit square millimetres, packing a considerable amount of tightly integrated DSP resources into very close proximity within an optimum vectorised data path. This area efficiency has been achieved through dynamic reuse — the scope of the domain of programmability was chosen to provide a level of silicon resources that can be dynamically re-used in the separate TX and RX DSP pipelines; in SC, SC-FDE, OFDM, control PHY as well as all modulation coding schemes (MCS), etc. The very high instruction level parallelism (ILP) is also key to the efficiency of the chip. Comparisons have shown that this technique provides greater than a four-fold advantage in both chip area and power efficiency compared with using a general SDR baseband platform that has been scaled to meet the WiGig performance requirements. Beyond 802.11ad Further development of the WiGig standard will be required in order to achieve the 30 Gb/s data rates that will soon be demanded. It is anticipated that further advanced techniques will be employed to extend the 802.11ad standard, specifically by the use of both 2 x 2 MIMO for parallel orthogonal spatial streams, and a technique called channel bonding, where multiple 2 GHz channels are aggregated to increase the size of the data ‘pipe’. Both MIMO and channel bonding will require a multiplication of the processing power already needed for the current WiGig standard. The scalability of the HYDRA baseband will facilitate a steady evolution of WiGig systems to control these new features. Moving to a 28 nm process, and increasing ½,  5/8,  3/4  ,  13/16     385  Mbps  –  4.62   Gbps     1760  MHz     ½,  5/8,  3/4  ,  13/16     693  Mbps  –  6.76   Gbps     2640  MHz     Table 1: Modulation schemes for WiGig/801.11ad modems. the number of PPUs used in parallel, would deliver the extra processing power required to control these features without significantly increasing the overall footprint. www.electronics-eetimes.com Electronic Engineering Times Europe October 2014 27


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