Page 58

EETE OCT 2014

ANALOGUE DESIGN Oscilloscope engine plugs into portable Apple products This month, Oscium is giving away three of its iMSO-204L dual analogue iOS oscilloscopes, worth USD400 each. Designed with native Lightning compatibility, the iMSO-204L transforms the iPad, iPhone, and iPod touch into an ultra-portable, two-channel oscilloscope. Since Apple changed its connector, Oscium has been working to bring native compatibility to its customers. The third generation of handheld engineering tools from Oscium, the iMSO-204L is the solution to the connector change, featuring two analogue and four digital channels, capable of 50 MSPS at a 5MHz bandwidth, and with a resolution varying from 200ns/div to 10s/div. The iMSO2 software supports single-shot waveform capture, pause and zoom through the touchscreen and AirPlay compatibility (so the oscilloscope display can be mirrored onto compatible projectors). The iMSO2 software is free in the Apple App Store, it is compatible with the iPhone 5C, iPhone 5S, iPhone 5, iPad Mini, iPad Air, iPad 4 and iPod touch 5th generation. Check the reader offer online at www.electronics-eetimes.com This device is the part of the calibration system that directs the flowing water into the collection tank while triggering a clock to determine the collection time. The water collected can be determined in terms of volumetric or gravimetric units. The calibration technique used for the set of measurements taken to obtain the multipoint compensation curve is based upon a reference flow meter that is traceable to this NIST gravimetric reference system. Calibration of each meter is unique, and usually performed by the meter manufacturer before shipment to the end customer. A 10-point compensation curve is applied to the plot of figure 3 to yield the plot of figure 6. Notice in figure 6 that the flow-rate accuracy is better than ±1% down to 0.5 liters per minute of flow rate. By comparing the plot of figure 6 to the plot of figure 2, it can be seen that the accuracy of the meter can be made to reflect the accuracy of the MAX35101. Power routing in analogue design By Keith Sabine Keith Sabine, product manager at EDA firm Pulsic, discusses the issues around power net routing for analogue blocks within integrated circuits. Automating analogue design requires that constraints such as symmetry and matching, noise coupling, and the use of shielding be part of the automated flow. Commercial routers capable at the device level can handle some of these types of constraints, but handling power net routing is typically done by planning manually. In the digital world, power distribution methodology is much easier. With row-based, standard cell placement and routing (P&R), and the availability of relatively many metal layers, power rings and meshes can be easily generated automatically. True, this can become more complicated as designers seek to use less power by using power switches and have multiple voltage domains, but there are well established EDA tools to help designers analyze and optimize power distribution schemes. For small analogue IP blocks, power routing can often be relatively simple. A common approach is to start with a “template” cell defining the desired block size, pin positions, and VDD/VSS rails, typically at the top and bottom of the block. However, even for relatively simple blocks, the power hookup to devices has generally been done manually. Actually, there is no reason why a mesh-type structure can’t be used; for example, two layers are shown in figure 1, which shows VDD/ VSS rails at the top and bottom of the block with an irregular H-shaped mesh in the centre. The key to achieving this is the ability to place and route devices, signal nets, and power nets simultaneously. Device S/D pins can directly strap to the power mesh to give a clean routing style. Widths of power tracks need to be considered carefully for analogue layout. As geometries get smaller, tapering of power nets may be required since uniform-width nets may be too wide for individual transistor tap-offs, but too narrow due to electromigration rules for higher current portions of the nets. In this case, careful consideration of current flow is required in order to size the net segments appropriately. Simulation results of transistor pin currents are required here in order to accurately model the current requirements of the power nets (and potentially the signal nets, too). Another common approach is to use combined power and guard rings/rails. The “variable mesh” approach can also be used here, although it becomes more complex as guard rings require single layer (i.e., wrong way) preferred directions. Again, device S/D pins can tap into guard rings to simplify local power routing. Fig. 1: Automated power routing mesh for an analogue block. A further development would be to support hierarchical power routing, where power pins on the lower-level blocks strap into the higher-level cells’ mesh. Once again, actual net widths need to be computed accurately for this approach. As can be seen, automated analogue routing presents challenges compared to digital power distribution. However, with new techniques and methodologies, automation is possible, and the goal of speedier design iterations can be achieved, enhancing productivity. Keith Sabine is Product Manager for Analogue Solutions at Pulsic Ltd – www.pulsic.com 46 Electronic Engineering Times Europe October 2014 www.electronics-eetimes.com


EETE OCT 2014
To see the actual publication please follow the link above