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EETE SEPTEMBER 2012

NEWS & TECHNOLOGY VLSI report Custom designed wireless links: what the 2012 VLSI Symposia had on offer By Julien Happich sponsored By tHe electron devices society, the solid state circuits society and the Japan society of Applied phys- ics, the 2012 vlsi symposia which took place last summer in Honolulu came as an opportunity for researchers to unveil new short-range wireless links and design concepts. striking examples include inductive rF coupling solutions for in-chip communications or through-skull neural sensing data collection. A team of researchers from the department of electrical en- gineering and computer sciences at the University of california, Berkeley, presented a 260GHz fully integrated cMos trans- ceiver for wireless chip-to-chip communication. designed in 65nm CMOS, the OOK modulation (On/Off Key) transceiver was demonstrated to transmit 10Gb/s over a range of 40mm. the tx/rx dual on-chip antenna array is implemented with half-width leaky wave antennas. each transmitter consists of a quadrupler driven by a class-d-1 pA with a distributed ooK modulator, and outputs +5 dBm of eirp. the receiver uses a Fig. 1: Sub THz wireless data-link setup. double balanced mixer to down-convert A paper from the Keio University, to a Vband IF signal that is amplified with Japan, disclosed the use of inductive a wideband iF driver and demodulated coupling, dubbed thruchip interface on-chip. (TCI) for inter-chip communication. In ef- fect, the idea is to use near-field wireless Another team from the same depart- connections between different 3D-chip ment presented a 65nm cMos-integrat- levels, instead of silicon vias. designed ed wireless neural sensor with a footprint as part of the digital cMos circuit of 0.125mm2 for minimally invasive integration, this solution is claimed to surgery, drawing only 10.5μW. be less expensive than using through this brain-machine interface consists silicon vias (TSVs) while offering similar of an array of electrodes that extend bandwidth. the researchers listed vari- vertically to reach relevant neurons, the ous issues with tsvs, including their wirelessly powered 65nm cMos ic inte- excessive footprint or the open fail- grating four 1.5μW amplifiers (6.5μVrms ures they cause due to thermal stress. input-referred noise for a 10kHz band- They looked at near-field communica- width) with power conditioning and tion at 50GHz in the 1mm range. the communication circuitry, and an induc- thruchip interface is described as being tive coupling receiver (RX) coil placed on surge-tolerant, thermally resilient, while top of the active circuitry to minimize the imposing no restrictions on the circuit device’s total footprint. position within multi-layer stacks. this this neural sensor is claimed to be Fig. 2: Conceptual system diagram of a multi-layer interconnection is said to able to record action potentials with wireless neural sensor. require only 3% of the footprint of con- enough resolution to ventional cMos i/os. it control a complex ro- was tested with stacks botic prothesis. data is of 128 dies, supporting then transmitted through a data rate per coil of the brain’s dura to a sub- 11Gb/s/ch and aggre- cutaneous interrogator. gating a data rate of the four 10-bit, 20kHz 8tb/s by arranging 1000 Adcs generate 800kbps channels within 6.4mm2 of neural data, which while drawing two orders is backscattered after of magnitude less power each sample is taken. than conventional high- the interrogator initiates speed memory links sampling and commu- such as ddr. nication by sending a this inter-chip, intra- 20kHz beacon. Fig. 3: ThruChip interface (TCI): (a) inductive coupling, (b) coil by multi-layer wires. stack communication 16 Electronic Engineering Times Europe September 2012 www.electronics-eetimes.com


EETE SEPTEMBER 2012
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