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Figure 1 shows the typical power consumption for the latest ultra-low power A/D converter from Analog Devices for various throughput rates. Also shown is a comparison of how utilisation of the power down mode of the device can provide additional power savings especially with lower throughput rates. the the power for a complete system is therefore the sum of AD7091r has an on-chip reference and therefore the through- each load capacitance by its switching frequency multiplied by put rate and utilisation of the power-down mode is determined the drive voltage. by the reference recharge time. Figure 1 also shows the typical power consumption if an external reference is used. when an external reference is used the reference recharge time does not apply, just the time to turn the ADc circuitry that was powered down back on. therefore the throughput rate where the power down mode can be used is greatly increased with an external where: reference. PL = Power to charge capacitive load the most common methods for initiating conversion requests cL = capacitive load in A/D converters are via a dedicated conversion input pin or VDriVe = Drive voltage controlled th--rough the serial interface. with a dedicated input f = Frequency of change pin a conversion is initiated by a falling edge of a convert start pin. the conversion is then controlled by an on-chip oscillator As the A/D converter drives the SDO pin and the host micro- and the result can be read back via the serial interface once the controller drives the /cS, /cOnVSt and ScLK the lowest power conversion is complete. therefore the conversion is always run consumption in both devices will be achieved by having a low at an optimum constant speed allowing the device to enter low pin capacitance in each device. power mode the moment a conversion is complete thus saving For the /cS and /cOnVSt pins the switching frequency is power. determined solely by the throughput rate. the ScLK frequency with A/D converters where the sampling instant is initiated as already discussed should be set to the maximum allowable by a /cS falling edge the conversion is controlled by the ScLK frequency to reduce power. this is not a contradiction as the signal. The SCLK frequency will affect the conversion time, important point is that the ScLK should not be free running throughput rate achievable and therefore the power consump- and should only be active for the minimum possible time to tion. the faster the ScLK time the faster the conversion time. Shorter conversion times mean the proportion of the time the device is in low power mode compared to normal mode in- creases and therefore significant power savings can be made. “In less than 5 days from running the tool, we improved the performance of our graphic rendering engine by 3x!”  - Terry West, Serious Integrated, Inc. where: tconv= time spent converting n = number of ScLK cycles to complete conversion fScLK = ScLK Frequency (Hz) Assuming 16 ScLK cycles to complete a conversion and re- sult read, a system sampling at 100 kSPS with a 30 MHz ScLK will spend 5.33% of the time converting (53.3 ms per second). Understand, Troubleshoot and Optimize the same system operating with a 10 MHz ScLK will spend 160 ms converting. therefore to achieve the optimum power World-leading trace visualization consumption the converter should be operated at the highest for a new level of insight allowable ScLK frequency. in FreeRTOS-based software! An important parameter when designing for low power that Highly efficient software recording. can often be overlooked is the capacitive load seen at the No extra trace hardware is needed. outputs pins. The pins most affected are the communication interface pins, such as the ScLK, /cS and SDO, as these i/O Download Free Edition are constantly changing state during the conversion process. and premium version evalution. the capacitive load seen at an output is the pin capacitance of Request a personal free web demo. the driver ic itself, the pin capacitance of the input pin plus the www.percepio.com PcB trace capacitance. the trace capacitance should generally be small, in the femtofarad range, and is not significant. The power required to charge a capacitive load is a function of the load, the drive volt- age and the frequency of change and is defined by the following equation. www.electronics-eetimes.com Electronic Engineering Times Europe September 2012 37


EETE SEPTEMBER 2012
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