Page 46

EETE SEPTEMBER 2012

DESIGN & PRODUCTS DATA ACQUISITION sumption. the pin capacitance is extremely low at 5pF maxi- mum. A wide input voltage range of 2.7 V to 5.25 V allow for integration into a range of applications not just battery powered. A separate Vdrive supply of 1.65 V to 5.25 V allows for maxi- mum system integration capabilities and reduced power. The AD7091R draws 349 μA typical at 3V Vdd when operat- ing at 1-MSPS. As is typical with A/D converters the AD7091r power scales with throughput so currents of 55 μA are achiev- able at 100 kSPS and 4.3uA when sampling at 10 SPS. Static current, when not converting but the reference is active, is 21.6 µA and in power down mode it draws only 264 nA. the AD7091r is available in a 10-lead MSOP or 10-lead LFcSP packages. Typical amplifiers to drive the AD7091R would be the AD8031 for fast throughput applications and the AD8420 for lower band- width applications. the quiescent current consumption of the AD8031 is 750 μA typical with a 2.7 V supply. The AD8420 has a quiescent current consumption of 70 μA typical when used with a 5 V supply. Figure 3 shows typical current consumption and typical Fig. 2: Typical interface power consumption battery life calculation for the AD7091r when supplied via a vs. capacitive load. cr2032 lithium battery. it can be clearly seen that as through- put decreases battery life can be greatly extended. propagate the result on the SDO line per sample and to control comparing the AD7091r to other A/D converters on the mar- the conversion process. this is device and resolution depen- ket significant savings can be achieved in the power budget. dant but 16 ScLK cycles per sample would be typical for SPi when compared against the nearest available competition, a interfaces. the frequency for the ScLK is therefore the number part with no internal reference, for a 1 MSPS throughput rate of cycles required multiplied by the throughput rate. the AD7091r achieves better than a 3x reduction in power the frequency of the SDO line is dependent not only on the consumption. Or 1 mw typical compared to 3.9 mw typical throughput rate but also the conversion result itself. while this is for a 3 V supply. this equates to extending the battery life of a not controllable it should be understood how it can affect power cr2032 battery by 400 hrs. when the need for an external volt- consumption. the highest power consumption will be when the age reference is included for the competitive device the savings result is a 101010… sequence. the lowest power consumption are further increased. will therefore be when the result is all 1’s or all 0’s. There are many benefits of a reduction in power consump- what is also apparent is that a lower throughput rate but tion other than increased battery life. Less heat is generated also a lower Vdrive voltage will also reduce power consumption which leads to smaller form factors. reliability improves due to considerably. A/D converters have either a single supply pin or the lower temperature stress. System costs can be lowered as separate supplies for the analogue circuitry and digital interface PcB size can be reduced due to the smaller components and circuitry. A separate Vdrive supply gives more design flexibility a reduction in components as there is no need for components and avoids the need for level shifters as the A/D interface volt- such as heatsinks. As outlined in this article, there are a sev- age can be matched to that of the SPi master. choosing the eral considerations that the system designer should take into lowest voltage available for Vdrive will correspond to the lowest account in order to optimise the power consumption of their system power consumption. designs. Figure 2 compares the typical power requirement of a stan- dard SPi interface with /cS, SDO and ScLK for varying capaci- tive loads for a VDriVe of 3V and 1.8V, a throughput rate of 100 kSPS, 16 ScLK cycles per conversion and a worst case SDO output of 1010… for a 12-bit A/D converter. Other typical components of an A/D converter design are a voltage reference and an operational amplifier. It goes without saying that these components should also be chosen carefully for low power. references are also available with power down modes to reduce consumption during periods of inactivity. the choice of amplifier is application dependant but the system throughput rate should be considered when selecting a device to ensure the best performance of the A/D converter is achieved and power is optimised. the ultra-low power A/D converter, AD7091r has been spe- cifically designed with low power designs in mind. It features a 12-bit A/D converter, SPi interface, on-chip precision 2.5V volt- age reference and achieves a sampling rate of 1 MSPS. conversions are initiated via a pin and an on-chip oscillator Fig. 3: Battery life vs. throughput for AD7091R. controls the conversion process ensuring optimum power con- 38 Electronic Engineering Times Europe September 2012 www.electronics-eetimes.com


EETE SEPTEMBER 2012
To see the actual publication please follow the link above