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EETE SEPT 2013

ReRAM startup bets on silver By Peter Clarke A resistive RAM non-volatile memory technology that could be embedded in SoCs and used in multilayered terabyte memory ICs is being brought to market by a well-backed and well-connected startup called Crossbar Inc. The company, based in Santa Clara, California, has a working array that it claims validates its silver-ion based technology as a replacement for traditional non-volatile memory. This working chip is a CMOS access controller monolithically integrated with a memory array. George Minassian, CEO of Crossbar, told E Times that his company’s embedded ReRAM technology will be available in 2014 and could be in the field in products such as microcontrollers in 2015. High-density monolithic memories based on the technology would then follow within a few quarters, he predicted. Crossbar’s memory technology is one of a number of alternative ReRAM offerings being researched by the industry. Most of these are trying to achieve equivalent or superior performance to NAND flash memory while being able to scale beyond the perceived two-dimensional limit for NAND flash at about 15 nanometers. Crossbar, founded in 2010, was formed to commercialize a body of memory device research based on metal-ion migration and filament formation within amorphous silicon that was being led by Professor Wei Lu at the University of Michigan. Professor Lu co-founded Crossbar and serves the company as chief technology officer. However, his amorphous silicon cross-point memory research was being nurtured by venture capital company Kleiner Perkins Caufield & Byers (KPCB) for a couple years prior to Crossbar’s formation, according to Minassian. The company has received $25 million in Series A and B rounds of funding and is backed by venture capital firms Artiman Ventures, KPCB, and Northern Light. Minassian told E Times that Crossbar plans to demonstrate its memory array prototype at the upcoming Flash Memory Summit Aug. 13 to 15 as a signal that it is ready to begin product development. According to briefing materials supplied by Crossbar, the memory is based on a silver top electrode over amorphous silicon over a polysilicon bottom electrode. The principle of operation is that a writing voltage causes silver ions to migrate through the silicon to form a filament that eventually can connect the top and bottom electrodes. A reverse voltage causes the ions to move and break the connection. Lower voltages can be used to “read” the connection as a 1 or 0. There are some similarities to the programmable metallization cell technology licensed to Adesto Technologies Corp. and others and being brought to market under the term conductive bridging RAM or CBRAM. Crossbar’s Fig. 2: Memory layers can be stacked demonstration array is substantial at a and processes are compatible with size of 1K by 1K, CMOS. Source: Crossbar Inc. and was fabricated in a commercial wafer fab using a 110-nm minimum geometry, Minassian said. He declined to name the fabricator. However, the company also has experience of making devices at geometries below 30nm and the filaments are thought to be less than 10nm in diameter, Minassian added. Voltages are modest, all below about 3.5 volts, and scale with geometry, Minassian said. The performance claims for the memory include 20 times faster write, 20 times lower power consumption, and 10 times the endurance of contemporary NAND flash memory. The read latency is about 20ns. The retention and endurance are tunable to a degree but Crossbar is quoting 10 years and 1 million cycles of endurance at sub-10nm geometry. An inherent blocking diode within the cross-point structure also helps avoid “sneak-path” problems while reading bits and keep the device structure simple and potentially close to the 4F2 theoretical minimum cell size. Other benefits include its simple construction, which means the memory is inherently capable of layered stacking - and more easily than 3-D flash, which requires a tapered vertical channel. Crossbar reckons that monolithic integration of up to eight memory layers on top of CMOS memory access circuitry should be “easy” and will allow multi-terabyte memory ICs. The company has already designed a memory controller circuit for a triple layer non-volatile memory as part of its development activity. “We’ve developed the CMOS controller logic and put memory layers on top,” said Minassian. The technology is also capable of multi-level cell configuration whereby multiple resistance points can be set and detected allowing multiple bits to be stored in a single cell. Crossbar plans to come to market in two phases, Minassian said. Initially, the company wants to license single-layer memory blocks as IP cores through foundries for use as embedded memory. After that, the company will develop stand-alone memories under its own brand, replacing NOR flash in code storage and NAND flash in data storage. “We are in discussions with foundries. It will take a couple more quarters to get the technology into wafer fabs but I see embedded memory in the market in 2015. Meanwhile, it will take two to three years from mid-2013 to get to stand-alone Fig. 1: The resistence-switching mechanism within Crossbar’s memory is based on the formation of a filament by the movement of silver ions from the top electrode within amorphous silicon. Source: Crossbar Inc. 10 Electronic Engineering Times Europe September 2013 www.electronics-eetimes.com


EETE SEPT 2013
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