028-029_EETE-VF

EETE SEPT 2013

TEST & MEASUREMENT DFT and test for safety-critical automotive ICs By Steve Pateras The growing quantity and sophistication of automotive electronics, particularly in safetycritical systems is driving higher quality and reliability requirements than ever. Not shipping defective parts has evolved from important to imperative. To address quality and reliability requirements, automotive IC makers are adopting new quality standards such as ISO 26262 and IEC 61508. Adhering to these standards, in turn, calls for some key updates to traditional design-for-test (DFT) methodologies. Among the updates are two new test methodologies that will become indispensable for safety- critical automotive electronics: cell-aware automatic test pattern generation (ATPG) and hybrid ATPG/logic built-in self-test (BIST). Cell-aware ATPG Cell-aware testing replaces traditional fault models, like stuck-at and transition delay, with a new model that develops the fault behavior from a layout-derived, transistor-level defect simulation of cells. Cell-aware ATPG significant improves the quality of testing of digital circuits over traditional ATPG, with minimal test cost increase – see figure 1. Why is cell-aware testing needed? Because while traditional fault models find the majority of defects, they can miss defects that occur within cells, which is a problem because that’s where roughly 50% of all defects occur. Also, traditional fault models are abstractions of defects, whereas cell-aware models are based on simulations of actual defects. Recently published results show the benefits of cell-aware test. A high-volume 350nm automotive IC design achieved an 88 DPM improvement after traditional test patterns had been applied. Typically, those additional defective parts would have been found through subsequent, but significantly more expensive, system-level tests. Further, the cell-aware testing detected parametric (delay) defects that allowed the designers to adjust design margins, thus reducing area and power consumption in the digital logic. Fig. 1: The cell-aware methodology improves test quality by detecting defects that occur within cells. Adding cell-aware testing to the DFT flow isn’t hard. Creating the cell-aware fault model involves a one-time characterization of a technology library. The cell-aware model can then be used on any design that uses that library. The automated characterization flow performs extraction from layout into a transistor-level netlist with parasitics for each cell in the library. Fig. 2: An illustration of CPU-based BIST access. Analog simulations then characterize the effects of potential layout-derived short and open defects to generate the cellaware model. Both single and dual-cycle analog fault simulation is performed in order to detect both static and delay-related defects. Steve Pateras is product marketing director within Mentor Graphics Silicon Test Solutions group and has responsibility for the company’s ATPG and DFT products – www.mentor.com – He can be reached at steve_pateras@mentor.com 28 Electronic Engineering Times Europe September 2013 www.electronics-eetimes.com


EETE SEPT 2013
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