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GLYN offers Bluetooth® 4.0 Smart Ready Module The BlueMod+SR from Stollmann is an extremely small (17x10x2.6mm) Bluetooth 4.0 qualified dual mode module with a wireless range of up to 100m. The module is designed for users who are looking for a cost-effective Bluetooth module, which supports classic Bluetooth basic rate (BR) and enhanced data rate (EDR) operations as well as the new Bluetooth low energy (LE) functionality. For basic rate operations it offers simple AT based Serial Port Profile (SPP) connections with full Secure Simple Pairing. For low energy operations the module offers a generic GATT interface. This interface allows the use of any GATT based profile. In addition to that it comes with Stollmann’s Terminal I/O profile. Terminal I/O allows transparent UART data transfer in low energy mode similar to SPP in basic rate mode. The module allows multiplexing solutions with BR/EDR and LE connections. It is also possible to tune the RF power to perfectly fit the application. The „BlueMod+SR“ is the next generation Bluetooth solution for cable replacement applications. Regardless if the application requires higher throughput or lower energy consumption, BlueMod+SR offers the best of both worlds. The module is designed and manufactured by Stollmann in Germany. It is available with integrated antenna or with antenna pin. GLYN GmbH & Co. KG www.glyn.com E-Mail: wireless@glyn.de The cell-aware fault models are written in a user-editable file and automatically incorporated into Mentor Graphics’ Tessent TestKompress pattern generation software. DFT engineers can also use that file to define any proprietary fault model that may be needed to improve quality levels for their specific process or application. Hybrid ATPG and logic BIST Another way to improve test efficiency and quality is by using a combination of ATPG compression and logic BIST techniques. In this hybrid approach, the on-chip logic used for the compression and the logic to implement the pseudo-random pattern logic BIST are combined and share DFT resources, like scan chains and on-chip clock control. This infrastructure allows any combination of compressed patterns and pseudo-random patterns to be applied. The hybrid approach gives you several ways to improve test efficiency during manufacturing test. First, you would use the BIST pseudo-random patterns to cover the faults that are easier to detect. You then don’t need to store ATPG patterns on the tester for these faults, which leaves more room on the tester for targeting faults that are more difficult to detect. The hybrid solution can also reduce the total test time for a complex, hierarchical design because each core is equipped with its own hybrid test infrastructure that allows it to be tested independently of other cores. When your cores can be tested independently, they can be tested in parallel, thus reducing overall test time. For example, consider an IC for an ABS and stability control system that has four cores. If you only used ATPG compression, then the four cores would have to share the available tester pattern application bandwidth. Either the cores could be tested sequentially using all available tester channels, or all cores could be tested in parallel with each core using a subset of the channels. However, if each core has both ATPG compression and logic BIST available, then the test for each core can be divided into two phases—ATPG in one phase and logic BIST in the other. With this separation, the entire chip can be tested in two phases. In the first phase, two cores use ATPG compression and the other two use logic BIST. In the second phase the situation is reversed. The advantage is that in each phase, only two cores are sharing all available tester channels, because logic BIST does not require patterns from the tester. This means the bandwidth to each core is doubled and the test time is reduced by half. The hybrid ATPG/logic BIST solution plays another critical role in addressing the reliability requirements defined by the ISO 26262 standard—the ability of logic BIST to provide in-system test of the device logic. The in-system capability of logic BIST can be combined with existing memory BIST capabilities to provide in-system test coverage for most, if not all, of the design. All of the BIST capabilities can generally be accessed through the standard IEEE 1149.1 TAP controller interface, but this dedicated interface is sometimes not accessible in-system. To accommodate in-system access, the TAP controller can be enhanced to also support a generic CPU interface that translates between parallel read/write CPU operations and the serial bit sequences required by the TAP protocol – see figure 2. Safety-critical automotive ICs need new test methods to meet the quality and reliability requirements of the ISO 26262 and other automotive electronics standards. With cell-aware test and hybrid ATPG/logic BIST, chip makers will be positioned to achieve high-quality test while controlling test costs even as device sizes and complexities continue to grow. www.electronics-eetimes.com Electronic Engineering Times Europe September 2013 29


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